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Dual-port static random access memory unit of half-refresh mechanism

A memory unit, static random technology, applied in the direction of static memory, digital memory information, information storage, etc., can solve the problems of large number of transistors, low density of memory cells, and reduced performance of transistors, so as to reduce the number of refreshes, increase the density of cells, cost reduction effect

Active Publication Date: 2015-07-22
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a dual-port SRAM unit with a half-refresh mechanism, which is used to solve the problem caused by the large number of transistors included in the SRAM unit in the prior art. Issues with lower memory cell density and reduced performance due to transistor scaling

Method used

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  • Dual-port static random access memory unit of half-refresh mechanism
  • Dual-port static random access memory unit of half-refresh mechanism
  • Dual-port static random access memory unit of half-refresh mechanism

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Embodiment 1

[0032] see figure 2, the present invention provides a dual-port SRAM unit with a half-refresh mechanism, the dual-port SRAM unit with a half-refresh mechanism at least includes: a monostable latch 10 and a monostable latch connected to the monostable latch 10 transmission gates; where,

[0033] The monostable latch 10 includes a pull-up transistor and a pull-down transistor. As an example, the pull-up transistor is a PMOS transistor, and the pull-down transistor is an NMOS transistor; the pull-up transistor is marked as PU, and the pull-down transistor is marked as PD.

[0034] The transmission gate is controlled by the first word line WL11, the second word line WL12, the third word line WL21 and the fourth word line WL22, and the transmission gate includes a first acquisition transistor, a second acquisition transistor, a third acquisition transistor and Fourth get the tube. As an example, the first acquisition tube, the second acquisition tube, the third acquisition tube...

Embodiment 2

[0049] This embodiment also provides a dual-port SRAM unit with a half-refresh mechanism, such as image 3 As shown, the dual-port SRAM unit of the half-refresh mechanism at least includes: a monostable latch 10 and a transmission gate connected to the monostable latch 10; wherein,

[0050] The monostable latch 10 includes a pull-up transistor and a pull-down transistor. As an example, the pull-up transistor is a PMOS transistor, and the pull-down transistor is an NMOS transistor; the pull-up transistor is marked as PU, and the pull-down transistor is marked as PD.

[0051] The transmission gate is controlled by the first word line WL11, the second word line WL12, the third word line WL21 and the fourth word line WL22, and the transmission gate includes a first acquisition transistor, a second acquisition transistor, a third acquisition transistor and Fourth get the tube. As an example, the first acquisition tube, the second acquisition tube, the third acquisition tube, and ...

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Abstract

The invention provides a dual-port static random access memory unit of a half-refresh mechanism. The dual-port static random access memory unit at least comprises a monostable latch and a transmission gate connected to the monostable latch; the monostable latch comprises an upper stay tube and a lower stay tube; the transmission gate comprises a first acquiring tube, a second acquiring tube, a third acquiring tube and a fourth acquiring tube. Compared with the traditional dual-port static random access memory unit, the quantity of unit transistors can be reduced, and the density of the dual-port static random access memory unit can be improved; compared with the traditional dynamic random access memory unit, the refresh times can be reduced; the size matching between the upper stay tube and the lower stay tube is not needed, as long as the first acquiring tube is matched with the third acquiring tube, and the second acquiring tube is matched with the fourth acquiring tube, thus the electric performance declining problem caused by the mismatching of the size of transistors inside the unit under the advanced process can be reduced; in addition, the process is compatible with the traditional ordinary CMOS logic process, so that the cost can be reduced.

Description

technical field [0001] The invention belongs to the technical field of memory design and relates to a static random access memory, in particular to a double-port static random access memory unit with a half-refresh mechanism. Background technique [0002] In the field of random access memory, compared with static random access memory, the data of dynamic random access memory needs to add a periodic refresh circuit due to the problem of charge leakage, but because of its high storage density, the cost is relatively low; The write speed is fast, no additional refresh circuit is required, and the peripheral circuit structure is relatively simple. [0003] With the development of integrated circuits, the system has more stringent requirements for the central processing unit (CPU), and the number of CPUs will be increased to provide computing power; high-speed data is often transmitted between CPUs, which requires higher memory speed, so it is often used in the CPU Internal and ...

Claims

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Application Information

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IPC IPC(8): G11C11/413
Inventor 陈静何伟伟罗杰馨王曦
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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