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Package assembly structure, forming method thereof, and package assembly method

A technology for assembling structures and packages, which is applied to semiconductor/solid-state device components, electrical components, and electrical solid-state devices. The effect of reducing the difficulty of position calibration

Active Publication Date: 2018-05-18
CHINA WAFER LEVEL CSP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The design of circular packages or other packages that are difficult to align has caused great problems for the later assembly of packages, resulting in large errors in the placement process and low yield of the formed devices

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] It can be seen from the background art that in the prior art, when the package is assembled later, the error of the mounting process is large, resulting in a low yield rate of the manufactured device.

[0034] After research, it was found that during the process of moving the package to the designated position for the placement process, the package has a displacement relative to the carrier board, resulting in a position deviation of the package that is sucked out. The position deviation refers to The most important thing is that, taking a certain point in the package as the reference coordinate, the difference between the position of the package before moving the package and the position of the package taken out; therefore, after the package is taken out and before the placement process, it is necessary to The package is aligned to improve the accuracy of the placement process.

[0035] When the package is a circular package or other packages that are difficult to determ...

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PUM

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Abstract

A package assembly structure and its forming method, and a package assembly method, wherein the package assembly structure includes: a carrier board, the bottom surface of the carrier board has several protrusions; a package placed on the bottom surface of the carrier board, Wherein, the package includes: a substrate placed on the bottom surface of the carrier board, the substrate has a front surface and a back surface opposite to the front surface, a number of blind holes are formed on the back surface of the substrate, and the protrusion is located at In the blind holes and interfitted with each other, a number of first pads are formed on the front of the substrate; for a chip located on the front of the substrate, the second surface of the chip is located on the front of the substrate, and the first surface of the chip has several The second welding pad; the two ends respectively have wires electrically connected to the first welding pad and the second welding pad; the plastic sealing layer located on the front surface of the substrate, the first surface of the chip and the surface of the side wall. The invention improves the accuracy of the placement process and effectively improves the yield rate of manufactured devices.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a package assembly structure, a forming method thereof, and a package assembly method. Background technique [0002] Grid array package (LGA, Land Grid Array) adopts point contact technology (contact), which uses metal contact package technology to replace the previous needle pin package technology, and makes a package with arrayed electrode contacts on the bottom surface key, and the surface mount technology (SMT, Surface Mounted Technology) can be used for mounting during assembly. [0003] The general process of LGA packaging includes: figure 1 as shown, figure 1 It is a top view structure schematic diagram of the package 10, the capacitor 1, the resistor 2, the inductor 3 and the chip 4 with different functions are placed in the corresponding functional area on the surface of the PCB substrate 5 through the SMT mounting process; The pads on the PCB subs...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/13H01L23/488H01L21/48H01L21/58H01L21/60
CPCH01L24/97H01L2224/48091H01L2924/181
Inventor 王之奇杨莹王蔚
Owner CHINA WAFER LEVEL CSP