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N-type ldmos device with trench gate structure and its process method

A process method, N-type technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of poor conduction performance and high electric field strength, and achieve enhanced drift region depletion, surface electric field reduction, The effect of increasing reliability

Active Publication Date: 2017-10-24
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This structure has a high electric field intensity on the surface and poor conduction performance

Method used

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  • N-type ldmos device with trench gate structure and its process method
  • N-type ldmos device with trench gate structure and its process method
  • N-type ldmos device with trench gate structure and its process method

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Embodiment Construction

[0021] The N-type LDMOS device of the trench gate structure according to the present invention, such as Figure 6 As shown, there is a trench in the N-type epitaxial layer 102 on the P-type substrate 101, and the gate oxide layer 104 is attached to the inner wall of the trench and filled with polysilicon to form the polysilicon gate 105 of the LDMOS device; the source region of the LDMOS device 106 is located in the P well 103, and the P well 103 also has a heavily doped P-type region 107; the surface of the substrate 101 has a field oxide layer 108; the N-type epitaxial layer 102 also has a P-type epitaxial layer 110, The depth of the P-type epitaxial layer 110 is 3-10 μm. The P well 103 is located in the P-type epitaxial layer 110 , and the bottom of the deep contact hole 109 passes through the P-type epitaxial layer 110 and is located in the N-type epitaxial layer 102 .

[0022] In order to solve the above problems, the process method of the N-type LDMOS device of the tren...

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PUM

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Abstract

The present invention discloses an N-type LDMOS device with a grooved-gate structure, which is characterized in that a P well is arranged in an N-type epitaxial layer on a P-type substrate, a source region of the LDMOS device and a heavily doped P-type region are arranged in the P well, the surface of the substrate is provided with a field oxide layer, a groove-type polysilicon gate is arranged in the N-type epitaxial layer, the inner wall of a groove is provided with a gate oxide layer; the N-type epitaxial layer is also provided with a P-type epitaxial layer therein, a deep contact hole penetrates the bottom of the P-type epitaxial layer and is arranged in the N-type epitaxial layer. Through adoption of the above structure, the electric field intensity of the surface of the device is reduced, and the device has higher breakdown voltage. The invention also discloses a process of the N-type LDMOS device with the grooved-gate structure.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to an N-type LDMOS device with a groove gate structure, and also relates to a process method for the N-type LDMOS device with a groove gate structure. Background technique [0002] DMOS is currently widely used in power management circuits due to its high voltage resistance, high current drive capability and extremely low power consumption. In the BCD process, although DMOS and CMOS are integrated in the same chip, due to the requirements of high withstand voltage and low on-resistance, the conditions of DMOS in the background area and drift area are shared with the existing process conditions of CMOS. , there is a contradiction between the on-resistance and the breakdown voltage, which often cannot meet the requirements of the switch tube application. In LDMOS devices, on-resistance is an important indicator. Therefore, in order to make high-performance LDMOS, it is necessary to ado...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/417H01L29/49H01L29/06H01L21/28H01L21/336
CPCH01L29/0684H01L29/4175H01L29/4916H01L29/66704H01L29/7825
Inventor 石晶钱文生
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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