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Verification method for DRAM (dynamic random access memory) system

A verification method, GDDR5 technology, applied in special data processing applications, instruments, calculations, etc.

Active Publication Date: 2015-08-26
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, high-performance DRAM image storage systems, such as GDDR5, encounter many challenges in testing and verification

Method used

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  • Verification method for DRAM (dynamic random access memory) system
  • Verification method for DRAM (dynamic random access memory) system
  • Verification method for DRAM (dynamic random access memory) system

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Embodiment Construction

[0023] The present invention will be specifically described below with reference to some embodiments shown in the accompanying drawings. In the following description, some specific details are described to provide a deeper understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, some well known process steps and / or structures have not been described in detail to avoid unnecessarily obscuring the present invention.

[0024] figure 1 A simplified exemplary diagram of a GDDR5 system coupled to a memory controller is shown.

[0025] exist figure 1 In the system shown, the memory controller consists of three components: INTF (interface), SEQ (sequencer), and PHY (physical layer).

[0026] INTF is a functional module that provides an interface to customer traffic. It does some mediation in the traffic of different clients.

[0027] SEQ ...

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Abstract

The invention provides a verification method for a DRAM (dynamic random access memory) system. Read and write data in the system are transmitted on two edges of a free-running differential clock. The verification method comprises steps as follows: monitoring a delay value in a data path, computing delay from instruction dispatching to read data returning in the data path, setting delay configuration in a to-be-tested design so as to be matched with full delay in the data path, and configuring a DRAM interface of the to-be-tested design based on delay setting. According to the method, a novel configuration time sequence is used in a simulation environment and a large quantity of computation resources are saved.

Description

technical field [0001] The present invention relates generally to integrated circuit system verification. In particular, the present invention relates to an authentication method for a dynamic random access memory (DRAM) system in which read and write data are transferred on both edges of a free-running differential forwarded clock, such as The GDDR5 (Graphics Double Data Rate, version5) system more specifically relates to a method for establishing a DRAM interface in verification. Background technique [0002] During the design phase of a semiconductor chip, engineers target production working models, rule out obvious defects and consider possible ways in which a product might fail. It's up to the verification engineers to judge their success. This can include testing pan-network connections, confirming that components are working correctly in sync, and troubleshooting specific issues pertaining to specific products. [0003] With yield and time-to-market of critical imp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 姚于斌彭瑞华王曦东
Owner ADVANCED MICRO DEVICES INC