High-speed and high-precision analog-to-digital conversion circuit
A technology of analog-to-digital conversion circuit and analog-to-digital converter, which is applied in the direction of analog/digital conversion calibration/testing, etc., can solve the problems of mismatching of sampling results and reduction of signal conversion accuracy, and meet the requirements of reducing gain and working bandwidth, reducing Design difficulty and effect of reducing system power consumption
Active Publication Date: 2015-09-09
厦门芯士力微电子有限公司
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The input signal is selected through the demultiplexer, and then the signal is introduced into different ADC (analog-to-digital converter) channels. Each channel has a separate sample and hold. By adjusting the sampling time of the clock, the sampling speed of each channel is relatively high. Low, each channel can achieve a higher sampling speed after processing in parallel. However, in this method, there is a mismatch in the sample-and-hold circuit of each channel, which will cause a mismatch in the sampling results of each channel, thereby reducing the signal conversion accuracy. In order to improve the signal conversion Accuracy, time interleaving circuits usually use various calibration methods to calibrate the mismatch
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[0023] The present invention will be further described below in conjunction with drawings and embodiments.
[0024] refer to figure 1 , a high-speed high-precision analog-to-digital conversion circuit, comprising: sequentially arranged sample-and-hold circuit, analog-to-digital conversion core circuit, data averaging circuit, output drive circuit, and digital output;
[0025] refer to figure 2 . In this embodiment, the analog-to-digital conversion core circuit includes a four-stage analog-to-digital conversion unit and a one-stage full parallel analog-to-digital converter. The analog-to-digital conversion unit at each stage includes two parallel-processed 2.5-bit secondary analog-to-digital converters with the same structure; the first-stage full-parallel analog-to-digital converter is a 4-bit full-parallel analog-to-digital converter.
[0026] refer to image 3 , Figure 4 , Figure 5 , Therefore, the analog signal is divided into two-way input signals after the unified...
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The invention provides a high-speed and high-precision analog-to-digital conversion circuit comprising a sampling and holding circuit, an analog-to-digital conversion core circuit, a data averaging circuit, an output driving circuit, and digital output, which are arranged in sequence. Analog signals are sampled and held in a unified manner and then divided into multiple channels of input signals. The analog-to-digital conversion core circuit is provided with at least one level of analog-to-digital conversion unit, and the at least one level of analog-to-digital conversion unit is internally provided with multiple parallel processing analog-to-digital converters corresponding to the multiple channels of input signals. According to the high-speed and high-precision analog-to-digital conversion circuit provided by the invention, the requirement on the gain and working bandwidth of an amplification circuit in the analog-to-digital conversion circuit is lowered, the power consumption of the system is reduced, and the design difficulty is reduced.
Description
technical field [0001] The invention relates to an analog-to-digital conversion circuit, in particular to a high-speed and high-precision analog-to-digital conversion circuit. Background technique [0002] The mainstream technologies for the high-precision design of high-speed analog-to-digital conversion circuits are time interleaving and digital calibration. The input signal is selected through the demultiplexer, and then the signal is introduced into different ADC (analog-to-digital converter) channels. Each channel has a separate sample and hold. By adjusting the sampling time of the clock, the sampling speed of each channel is relatively high. Low, each channel can achieve a higher sampling speed after processing in parallel. However, in this method, there is a mismatch in the sample-and-hold circuit of each channel, which will cause a mismatch in the sampling results of each channel, thereby reducing the signal conversion accuracy. In order to improve the signal conver...
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IPC IPC(8): H03M1/10
Inventor 林海军
Owner 厦门芯士力微电子有限公司