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Wafer based beol process for chip embedding

A semiconductor and contact structure technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve problems such as not suitable for blade packaging

Inactive Publication Date: 2015-10-07
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, a common advantage has been found, for example, in relying on SFETx (x stands for 3, 4 or 5) technology (also known as "dual poly" (i.e. a design with two electrodes insulated from each other in a trench) or its trademark Optimos). The chip concept is not suitable for blade packaging due to the nature of the metallization and / or the passivation process, and therefore a solution to this problem would be desirable

Method used

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  • Wafer based beol process for chip embedding
  • Wafer based beol process for chip embedding
  • Wafer based beol process for chip embedding

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Embodiment Construction

[0014] The following detailed description refers to the accompanying drawings, which show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0015] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or superior to other embodiments or designs.

[0016] Blade packaging can be understood as the application of printed circuit boards (PCBs) in semiconductor manufacturing technology. During the packaging process, the die may be attached to a leadframe by soldering so that the backside of the die may be electrically accessible. The front side of the die can also be electrically contacted through the metal layer.

[0017] FIG. 1 shows a vertical structure of a field effect transistor 100 . The vertical field effect transistor 100 can be manufactured according to the SFET5 technology s...

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Abstract

In various embodiments a semiconductor device is provided, including a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.

Description

technical field [0001] Various embodiments relate to a wafer-based BEOL for chip embedding (back end of line). Background technique [0002] Packaging is the final stage of semiconductor device fabrication in which small pieces of processed semiconductor, ie chips, are placed in a supporting package that protects them from physical damage and erosion. The package (commonly referred to as the "package") supports the electrical contacts that connect the chip to the circuit board. [0003] Standard packaging processes are usually based on bonding and molding. The interconnection is achieved through an electrochemical process and the die is protected with a laminate material. [0004] In a new packaging concept, also called Blade packaging, the chip is attached to a circuit board. Both the front side and the back side of the chip are in electrical contact with the lead frame via the metal layer. The blade package is a vertical transistor package optimized for high current re...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/45
CPCH01L29/7813H01L21/283H01L23/3157H01L23/3171H01L29/1095H01L29/45H01L29/66712H01L2924/0002H01L29/456H01L29/66734H01L29/41741H01L29/66666H01L29/7827H01L23/485H01L23/53238H01L2924/00
Inventor P·加尼策尔M·雅各布A·策希曼
Owner INFINEON TECH AG