A kind of caching system and method

Abstract

The present invention provides a cache system and method, which can fill the instruction and corresponding data into the high-speed memory directly accessible by the processor core before the processor core executes the instruction when applied in the field of processors, and do not need The processor core provides an instruction address or a data address, and directly controls the high-speed memory to provide instructions or data to the processor core according to the feedback information generated by the execution of the instruction by the processor core, so that the processor core can be used almost every time in the The required instructions are obtained in the high-speed memory to achieve a very high cache hit rate; in addition, the emission of the instruction is scheduled according to the program flow information stored in the cache system, and the time point of instruction emission is determined according to the instruction sequence and distance information , so as to realize instruction multi-issue.

Description

technical field [0001] The invention relates to the fields of computer, communication and integrated circuit. Background technique [0002] In a processor system that includes a pipeline, the pipeline is usually suspended due to factors such as Cache Miss, Control Hazard, and Data Hazard, thereby affecting the performance of the processor system. [0003] Cache misses generally fall into three categories: forced misses, conflict misses, and capacity misses. Using a set-associative cache structure and increasing the number of cached way groups can reduce conflict misses, but it is limited by power consumption and speed (for example, because the multi-way set-associative cache structure requires all way groups to be addressed by the same index content and tags Read and compare at the same time), the number of road groups is difficult to exceed a certain number. Existing cache prefetching techniques can usually solve some of the problems of missing conflicts and missing capac...

AI Technical Summary

Problems solved by technology

Since data read instructions and data storage instructions do not involve arithmetic and logic operations, the greater the proportion of such instructions, the lower the utilization rate of the processor's operation unit, and the less the processor's computing power can be fully utilized.

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