A cascode fully integrated low-leakage linear regulator circuit

Abstract

The invention discloses a cascode fully integrated low-dropout linear voltage regulator circuit. According to the invention, a ascode current source is introduced to replace a conventional single transistor current source in a Cascoded Flipped Voltage Follower-Low-dropout (CAFVF-LDO) circuit, which increases the loop gain of the CAFVF-LDO circuit under heavy load condition; at the same time based on the structure features of the Cascode Current Source (CCS), a cascode compensation technology is introduced. Compared with the conventional CAFVF-LDO, the circuit of the invention, by means of a very small on chip compensation capacitor, realizes stable operation under a much lower load current, and a cascode compensation capacitor also expands the Unity-Gain-Frequency (UGF) of the LDO circuit under heavy load condition, and further improves load transient response of the circuit. The cascode fully integrated low-dropout linear voltage regulator circuit can be widely applied to the field of integrated circuits.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a cascode fully integrated low-leakage linear regulator circuit. Background technique [0002] Low-dropout (LDO) linear regulator is a low-cost power management solution for System-on-a-chip (SoC) applications. figure 1 Shown is a schematic structural diagram of a traditional LDO regulator, which consists of an operational amplifier driving a power transistor plus a feedback resistor network. In order to achieve stability, the output often needs to be connected with a suitable equivalent series resistance (R esr ) load capacitance. Compared with the traditional LDO regulator, the recent single transistor control (Single Transistor Control, STC) LDO regulator circuit based on the reverse voltage follower structure (Flipped Voltage Follower, FVF) has a simple structure and excellent transient response characteristics. And other advantages, thus getting more and more attention,...

AI Technical Summary

Problems solved by technology

However, the STC-LDO regulator has two major disadvantages: first, due to the simple circuit structure, the loop gain is low (maybe less than 40dB), which makes the load regulation poor; second, if figure 2 As shown, the STC-LDO regulator has a minimum load limit, when the load is low, the power tube M P The gate voltage needs to be increased to reduce the overdrive voltage to reduce the output current, and at this time the control transistor M C It is likely to enter the linear region, thereby reducing the output voltage accuracy of the regulator

[0009] It can be seen from formula (3) that the output impedance of the CCS as a load is the same as that of a single transistor current source at this time, and there is no effect of gain increase

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