Chip dram pad layout structure to improve package compatibility

Abstract

The invention discloses a chip DRAM (dynamic random access memory) pad arrangement structure for improving encapsulation compatibility. The DRAM pads of a chip include a plurality of first pads, a plurality of second pads and a plurality of third pads; the plurality of first pads are arranged at intervals so as to form an inner-row pad group; the plurality of second pads are arranged at intervals so as to form a middle-row pad group; the plurality of third pads are arranged at intervals so as to form an outer-row pad group; the inner-row pad group is located between the center of the chip and the middle-row pad group; the middle-row pad group is located between the inner-row pad group and the outer-row pad group; and the outer-row pad group is located between the middle-row pad group and the boundary of the chip. The chip DRAM pad arrangement structure for improving encapsulation compatibility has the advantages of strong compatibility and no need for encapsulation cost increase, and can satisfy wire bonding requirements of frame-class encapsulation such as WB BGA encapsulation and eLQFP encapsulation.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a chip DRAM pad arrangement structure for improving packaging compatibility. Background technique [0002] Nowadays, the electronic system market is highly competitive. How to quickly respond to market demand and output lower-cost electronic products has become an important factor in winning the competition. For users, they hope to buy cost-effective products that meet actual needs. For solution providers, being able to provide customized product solutions for high-level, middle-level and low-level user needs will increase sales profits and reduce production and development costs. For an AP (Application Processor, application processor) manufacturer, being able to launch a highly compatible and stable IC (Integrated circuit, integrated circuit) design will shorten the development cycle, reduce design costs, and improve efficiency. [0003] At present, mainstream chip pac...

AI Technical Summary

Problems solved by technology

The existing chip pad layout design generally only considers supporting a single chip package

The key point of chip package compatible design is chip pad design. The existing pad design only supports single chip package, which makes the compatibility between SIP design and single chip package design low.

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