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Multiple times programmable memory and its operating method

An operation method and memory technology, applied in static memory, read-only memory, information storage, etc., can solve the problems of large area, large memory area, unfavorable large-capacity storage applications, etc., and achieve the effect of reducing area and improving voltage coupling efficiency

Active Publication Date: 2018-12-07
ZHUHAI CHUANGFEIXIN TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This memory cell structure requiring a larger area of ​​field oxygen isolation regions makes the entire area of ​​the memory cell larger, so the area of ​​the memory cell array composed of such larger area memory cells is also very large, resulting in the formation of memory cells. Large area, not conducive to mass storage applications

Method used

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  • Multiple times programmable memory and its operating method
  • Multiple times programmable memory and its operating method
  • Multiple times programmable memory and its operating method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0070] see figure 2 , figure 2 is a schematic diagram of the storage unit structure in Embodiment 1 of the present invention, such as figure 2 As shown, the storage unit includes a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3, wherein the first MOS transistor M1 is a capacitive coupling transistor, the second MOS transistor M2 is a capacitive tunneling transistor, and the third MOS transistor M2 is a capacitive coupling transistor. The MOS transistor M3 is a storage transistor. It should be noted that the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 are all single-layer floating gate transistors, and the gate of the first MOS transistor M1, the gate of the second MOS transistor M2 and all The gates of the third MOS transistor M3 are connected together through polysilicon. It can also be understood that the three transistors M1 to M3 share a polysilicon gate.

[0071] The source and drain of th...

Embodiment 2

[0111] The storage unit described in the second embodiment is based on the storage unit described in the first embodiment with the fourth MOS transistor M4 added. The fourth MOS transistor M4 functions as a selection control transistor. For its specific structure, please refer to Figure 7 .

[0112] Such as Figure 7 As shown, the storage unit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a fourth MOS transistor M4. Wherein, the function and connection relationship of the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 are basically the same as those described in Embodiment 1. For the sake of brevity, no detailed description is given here. See the description of Example 1. In this embodiment, only the differences are described emphatically.

[0113] In the embodiment of the present invention, the fourth MOS transistor M4 is a single-gate MOS transistor, and the gate of the fourth MOS tr...

Embodiment 3

[0120] Figure 9 is a schematic diagram of the structure of the storage unit in Embodiment 3 of the present invention, such as Figure 9 As shown, the memory cell includes an NMOS transistor N1 and a PMOS transistor P1, the NMOS transistor N1 and the PMOS transistor P1 are both single-layer floating gate transistors, and the NMOS transistor N1 is a source-drain through transistor. Wherein, the gate of the NMOS transistor N1 and the gate of the PMOS transistor P1 can be connected together through a polysilicon gate, the source and drain of the NMOS transistor N1 are connected to the first voltage terminal V1, and the PMOS transistor P1 The source of the PMOS transistor P1 is connected to the second voltage terminal V2, the drain of the PMOS transistor P1 is connected to the third voltage terminal V3, and the drain of the PMOS transistor P1 is also connected to the sense amplifier. Wherein, the well containing the NMOS transistor N1 is not connected to the first voltage termina...

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Abstract

The invention provides a memory capable of being programmed many times and an operating method thereof. Each storage unit in the memory at least comprises a first MOS tube, a second MOS tube and a third MOS tube, wherein the first MOS tube, the second MOS tube and the third MOS tube are single-layer floating gate transistors, when the first MOS tube and the second MOS tube are MOS tubes of the same type, the first MOS tube and the second MOS tube are source-drain penetrating tubes, when one of the first MOS tube and the second MOS tube is a PMOS tube, and the other of the first MOS tube and the second MOS tube is an NMOS tube, the NMOS tube is a source-drain penetrating tube. As the source-drain penetrating tubes are utilized, the capacitance coupling efficiency of the memory is improved, and the area of each storage unit is reduced by means of the memory structure, which is beneficial for large-capacity storage application.

Description

technical field [0001] The invention relates to the field of semiconductor memory devices, in particular to a multi-time programmable memory and an operation method thereof. Background technique [0002] In the application field of multiple programmable embedded non-volatile memory, there are mainly eFlash and EEPROM memory based on floating gate technology and multiple programmable (MTP) memory based on CMOS single gate technology. [0003] The memory technology based on the floating gate process is mature, with high integration and large storage capacity, but compared with the standard CMOS process, it needs to increase the mask plate and process steps, which greatly increases the cost of the SOC chip. [0004] The MTP memory based on the single-gate process is fully compatible with the standard CMOS process and does not increase any process cost. However, the memory cell in the currently applied single-gate MTP memory is composed of 4 PMOS transistors, and its structural...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/10
Inventor 王志刚李弦
Owner ZHUHAI CHUANGFEIXIN TECH CO LTD