Double-tube-core Trench MOSFET and processing method thereof

A processing method and dual-die technology, applied in the manufacture of transistors, electrical components, semiconductor/solid-state devices, etc., can solve the problem of large area of ​​TrenchMOSFET, and achieve the effect of increasing the number of effective dies, reducing the area and reducing the cost.

Active Publication Date: 2015-12-30
FUJIAN FUXIN ELECTRONICS TECH CO LTD
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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a TrenchMOSFET with a dual-tube core and a

Method used

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  • Double-tube-core Trench MOSFET and processing method thereof
  • Double-tube-core Trench MOSFET and processing method thereof
  • Double-tube-core Trench MOSFET and processing method thereof

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Embodiment Construction

[0023] In order to describe the technical content, structural features, achieved goals and effects of the present invention in detail, the following will be described in detail in conjunction with the embodiments and accompanying drawings.

[0024] see Figure 2 to Figure 6 , The present invention provides a dual-die Trench MOSFET, wherein the MOSFET is a metal-oxide semiconductor field-effect transistor, referred to as a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). It includes an N+ substrate layer 1, an N- epitaxial layer 2 is arranged on the N+ substrate layer 1, and a P-body layer 7 is respectively arranged in the middle and both sides of the N- epitaxial layer. The P-body layer may be formed from the N- epitaxial layer of the P-body layer through B+ implantation. The left and right sides of the P-body layer 7 are respectively provided with a first trench 3 and a second trench 4, and between the first trenc...

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Abstract

The invention provides a double-tube-core Trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and a processing method thereof. The double-tube-core Trench MOSFET comprises an N+substrate layer, wherein an N-epitaxial layer is arranged on the N+substrate layer; P-body layers are respectively arranged in the middle and on the two sides of the N-epitaxial layer; a first Trench and a second Trench are respectively arranged on the left side and the right side of each P-body layer; discontinuous P-body layers are arranged between the first Trenches and the second Trenches; the first Trenches and the second Trenches run through the P-body layers; Poly structures are arranged in the first Trenches and the second Trenches; first Drain zones are arranged at the upper parts of P-body layers on the left sides of the first Trenches. According to the invention, independent Ring structures of the two MOSFETs are combined into a Ring structure, so that the advantages of reducing the area of the single MOS, increasing the number of the single effective tube core and reducing the cost are realized on the premise of not influencing the performance of the product.

Description

technical field [0001] The invention relates to the field of transistors, in particular to a dual tube-core TrenchMOSFET and a processing method thereof. Background technique [0002] An existing low-voltage Trench (trench) MOSFET product consists of two parts, the Cell area (primary cell area) in the central area and the Ring area (voltage resistance area) around it. The Cell area mainly plays the role of current conduction, and the Ring area The area is mainly to increase the breakdown voltage of the product. The Cell area is the current path when the device is turned on, and the Ring area around the cell area is used to increase the lateral breakdown voltage of the device. [0003] In order to reduce the packaging cost of some low-voltage TrenchMOSFET products, it is usually necessary to package two TrenchMOSFET tubes together, and the two MOSFETs can be controlled separately, so when designing the layout of the low-voltage TrenchMOSFET, usually two MOS tubes are placed s...

Claims

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Application Information

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IPC IPC(8): H01L27/088H01L21/8234H01L29/06
Inventor 陈虞平胡兴正王熹伟刘海波孙晓儒
Owner FUJIAN FUXIN ELECTRONICS TECH CO LTD
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