A kind of dual-bit sonos memory and its compiling, erasing and reading method

Abstract

The invention discloses a dual-bit SONOS memory, which comprises: a P-type silicon substrate with an N-type doped source terminal, a drain terminal and an N channel in the substrate; and a substrate built between the source and the drain terminals. The gate structure includes a first silicon dioxide layer, a silicon nitride layer, a second silicon dioxide layer and a polysilicon control gate from bottom to top, and the silicon nitride layer includes the first storage The bit and the second storage bit near the source side are used to store charges; adopt low power consumption band tunneling hot hole injection programming, channel FN electron tunneling and erasing, and use back gate bias to assist hot air Hole injection can make the traditional SONOS device structure have a smaller gate length, which solves the problem of high power consumption of the existing channel hot electron injection compilation, and the dual-bit storage SONOS can have higher storage density and storage capacity. Great advantage in markets where mass storage is prevalent.

Description

technical field [0001] The present invention relates to the technical field of semiconductor memory, more specifically, to a double-bit SONOS memory and methods for compiling, erasing and reading it. Background technique [0002] For the NOR flash memory unit, the most important factor limiting the further reduction of its size is the further shortening of the gate length. This is mainly because the compilation method of channel hot electron (CHE) injection used in NOR flash memory cells requires a certain voltage at the drain of the device, and this voltage has a great impact on the penetration of the source and drain. Therefore, channel hot electron (CHE) injection is not suitable for short-channel devices. Another problem is that NOR flash memory is limited by the programming rate compared with NAND and AND data storage devices. According to the prediction of the document "G. Servalli, et al., IEDM Tech. Dig., 35_1, 2005", the physical limit of the gate length reduction...

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Problems solved by technology

[0016] The purpose of the present invention is to overcome the above-mentioned defects existing in the prior art, provide a double-bit SONOS memory and its compiling, erasing and reading methods, which can solve the problem of high power consumption during the existing channel hot electron injection compiling, and It can solve the defects of complex circuit structure, slow reading, writing and erasing speed and high reliability requirements in traditional floating gate multi-bit storage technology

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