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Thin film transistor array substrate, preparation method thereof and display device

A thin-film transistor and array substrate technology, applied in the display field, can solve problems such as ITO breakage and easy corrosion of signal lines

Inactive Publication Date: 2016-01-06
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present invention aims at the problems that the ITO connected to the signal line in the frame area is prone to fracture and the signal line is easily corroded, and provides a thin film transistor array substrate, a preparation method thereof, and a display device

Method used

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  • Thin film transistor array substrate, preparation method thereof and display device
  • Thin film transistor array substrate, preparation method thereof and display device
  • Thin film transistor array substrate, preparation method thereof and display device

Examples

Experimental program
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Effect test

Embodiment 1

[0030] This embodiment provides a thin film transistor array substrate, including: a display area and a frame area surrounding the display area, and the frame area includes:

[0031] Substrate;

[0032] A signal line, an insulating layer, and a conductive layer are sequentially formed on the substrate, the conductive layer is connected to the signal line through a via hole in the insulating layer, and between the conductive layer and the signal line in the via hole, A corrosion-resistant conductive layer is provided.

[0033] In the TFT array substrate of this embodiment, the corrosion-resistant conductive layer is placed between the conductive layer in the via hole and the signal line to support the conductive layer, which can prevent the conductive layer from breaking and avoid abnormal display. At the same time, it can also isolate the signal line to prevent the signal line from being corroded. The thin film transistor array substrate of the present invention is suitable ...

Embodiment 2

[0035] This embodiment provides a thin film transistor array substrate, including: a display area and a frame area surrounding the display area, such as image 3 , Figure 4 As shown, the border area includes:

[0036] Substrate;

[0037] A signal line, an insulating layer and a conductive layer 1 are sequentially formed on the substrate. The conductive layer 1 is connected to the signal line through a via hole in the insulating layer, and between the conductive layer 1 and the signal line in the via hole, a resistance The conductive layer 51 is etched.

[0038] In the thin film transistor array substrate of this embodiment, the corrosion-resistant conductive layer 51 is placed between the conductive layer 1 and the signal line in the via hole to support the conductive layer 1, which can prevent the conductive layer 1 from breaking and avoid abnormal display. At the same time, it can also isolate the signal line to prevent the signal line from being corroded. The thin film...

Embodiment 3

[0053] This embodiment provides a method for preparing the thin film transistor array substrate of Embodiment 2, and the specific process steps are as follows:

[0054] S1 forms the gate of the display area, and simultaneously forms the gate line 3 of the frame area;

[0055] S2 depositing the first insulating layer 21, and forming the active layer of the display area;

[0056] S3 forms a pixel electrode;

[0057] S4 forms the source and drain;

[0058] S5 forms the second insulating layer 22 and the corrosion-resistant conductive layer 51;

[0059] S6 forms the common electrode and simultaneously forms the ITO conductive layer 1 in the frame area.

[0060] The preparation method of this embodiment is simple and practical. This embodiment is only carried out with the 6Mask (gate-active layer-pixel electrode-source-drain-second insulating layer 22-pixel electrode) process commonly used in the existing planar electric field type. For illustration, it is also applicable to th...

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Abstract

The invention provides a thin film transistor array substrate and belongs to the display technical field. With the thin film transistor array substrate adopted, the problems of high possibility of fracture of an ITO which is located in a frame area and is connected with a signal line and high possibility of corrosion of the signal line can be solved. According to the thin film transistor array substrate of the invention, a frame area comprises a substrate as well as a signal line, insulating layers and an electric conduction layer which are formed on the substrate sequentially; the electric conduction layer is connected with the signal line through a via hole in the insulating layers; and in the via hole, a corrosion-resistant electric conduction layer is arranged between the electric conduction layer and the signal line. The corrosion-resistant electric conduction layer is laid between the electric conduction layer and the signal line in the via hole, so as to support the electric conduction layer, and therefore, the fracture of the electric conduction layer can be prevented, and abnormal display can be avoided; and the signal line can be isolated, so that the signal line can be protected from being corroded. The thin film transistor array substrate of the invention is suitable for various kinds of display devices.

Description

technical field [0001] The invention belongs to the field of display technology, and in particular relates to a thin film transistor array substrate, a preparation method thereof, and a display device. Background technique [0002] The thin film transistor array substrate includes a display area and a frame area surrounding the display area, wherein the frame area is such as figure 1 , figure 2 As shown, it is used to set various signal lines (gate line 3 or data line 4) and form a region connected with a control chip or a flexible printed circuit board. Specifically, the conductive layer 1 in the frame area is generally formed synchronously with the electrodes (common electrodes or pixel electrodes) in the display area, and its material is usually ITO (indium tin oxide). The conductive layer 1 passes through the insulating layer ( figure 1 The first insulating layer 21 and the second insulating layer 22; figure 2 The via hole in the second insulating layer 22) connects...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/77H01L27/15G09G3/20
CPCH01L27/1214G09G3/20H01L21/77H01L27/124H01L27/156
Inventor 高山黄炜赟龙跃
Owner BOE TECH GRP CO LTD
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