A zero-order image suppression method and circuit for digital hologram
A digital hologram and hologram technology, applied in image communication, color TV parts, TV system parts, etc., can solve the problem of slow data processing speed, loss of information optical parallel processing capability, and inability to meet the intelligence of digital holographic systems. The application development needs of miniaturization, miniaturization, and light weight are solved, so as to restore the parallel processing capability and improve the processing efficiency.
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Embodiment 1
[0079] see Figure 4 to Figure 6 A circuit for realizing zero-order image suppression of digital holograms based on an FPGA integrated chip; comprising an image sensor CCD3, a DSP main control processor 1 and a zero-order image suppression circuit 2 connected in sequence;
[0080] Described zero-level image suppressing circuit 2 comprises the FPGA integrated chip that is connected with DSP main control processor 1; The buffer memory 23, pixel data processor 21 and filter circuit 22 that are connected successively are integrated on the described FPGA integrated chip; The buffer memory 23 is connected with the DSP main control processor 1 and the pixel data processor 21 respectively;
[0081] The pixel data processor 21 includes a sequentially connected serial-in-parallel module 211 and a pixel data refresh module 212; the serial-in-parallel module 211 is connected to the buffer memory 23; the pixel data refresh module 212 is connected to a filter Circuit 22 is connected;
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Embodiment 2
[0092] see Figure 1 to Figure 3 , a method for realizing zero-order image suppression of a digital hologram based on the circuit structure of Embodiment 1; assuming that the order of the two-dimensional FIR filter used for off-axis digital hologram zero-order image suppression is R*R; specifically comprising The following steps:
[0093] (1) acquiring digital hologram data; performing frame window division on the digital hologram data according to the order of the filter, and acquiring frame window data;
[0094] The digital hologram data transmitted by the DSP main control processor 1 is first sent to the FIFO queue memory for buffer storage. Here, the preferred FIFO queue memory only stores one frame of hologram pixel data at a time, so as to improve the image pixel data processing efficiency;
[0095] In the FIFO queue memory, the digital hologram data is divided into a frame window according to the R column, and the frame window moves from left to right in the digital ho...
Embodiment 3
[0104] Provide a specific process for realizing zero-order image suppression of digital holograms based on Embodiment 1 and Embodiment 2;
[0105] The off-axis digital hologram is the most commonly used holographic recording method when the angle between the object light and the reference light meets certain conditions, and there is no mutual interference in the diffracted light.
[0106] The optical path of the recording process of off-axis digital holography is as follows: Figure 7 shown.
[0107] Figure 7 The light intensity of the middle holographic plane is the object light U(x H ,y H ) and reference light R(x H ,y H ) interference result, which can be expressed as:
[0108] I H (x H ,y H )=[U(x H ,y H )+R(x H ,y H )]·[U(x H ,y H )+R(x H ,y H )] * (1)
[0109] to me H (x H ,y H ) direct digital reconstruction, there will be zero-order diffraction images, original images and conjugate images on the reconstructed image plane, and the zero-order imag...
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