Cache consistency limit test method

Abstract

The present invention provides a cache consistency limit test method. The method comprises the steps of: performing size and structure configuration of Cache, wherein granularity, memory access order and a memory access Cache entry address of the Cache consistency limit test are determined according to Cache size, Cache line length, quantity of connected link groups and a consistency strategy, and the whole Cache is not traversed; setting an initial value and a data reduction operation for precise error location, wherein the address is used as the initial value, and the data reduction operation adopts a migration operation with least beats; setting a multi-granularity high-density memory access mode, wherein Cache operation takes Cache line as a unit, and different processors perform memory access on the same Cache in a parallel process simultaneously or alternately; and setting Cache protocol verification related to the system.

Description

technical field [0001] The present invention relates to the technical field of computer, more specifically, the present invention relates to a kind of Cache (high speed cache) coherence limit test method. Background technique [0002] The correctness verification of the Cache consistency protocol is an important stage of computer system engineering. The problem to be solved by the limit test is how to pass high-density and high-intensity tests in a limited space and time to expose the Cache consistency in a dynamic state. Protocol issues, and errors can be quickly reproduced and accurately located. The consistency limit test needs to solve four technical problems: configure the scale and structure of the Cache and the Cache protocol to facilitate the verification design of the Cache protocol; design the initial value and data restoration operation for precise error location; multi-granularity high-density memory access Design; Cache protocol verification design. [0003] I...

AI Technical Summary

Problems solved by technology

Common applications include calculations, which are performed between registers. Programs mixed with calculations have insufficient memory access density, and the memory access mode of a topic is often relatively single, which makes it difficult to cover all the functions of the Cache coherency protocol.

[0004] Even though the space occupation is not the main problem of the Cache test, sequential and continuous access traverses a space twice the size of the Cache. There are several shortcomings: (1) The memory access density is not enough; (2) The memory access mode is single

Images