[0024] The present invention will be further explained below in conjunction with the drawings.
[0025] The invention provides a dynamic ad hoc network wireless communication device, which is based on a high-speed data processing "CPU and FPGA" architecture design, which can increase the data processing speed, such as figure 1 As shown, the present invention includes a central processing module, a data processing module, an SDRAM storage module, an integrated service interface management module, a data processing module, a modulation module, a demodulation module and a frequency conversion module.
[0026] Among them, the central processing module is realized by a central processing chip. In the present invention, the Coldfire V4 central processing chip is preferably used. The central processing chip has a 410MIPS core processing speed, 16KB instruction cache, 16KB data cache and 32KB SRAM configuration. The data processing module is designed with Xilinx's Virtex-5 FPGA processing chip. The Virtex-5 chip has multiple hard IP cores, including: powerful 36kbit structured RAM/FIFOs; second generation 25bitX18bit multiplication DSP structure; Field input/output port impedance matching technology; source synchronous interface technology; enhanced DCM clock formation technology.
[0027] The central processing module is the core processing module of the entire design, which mainly implements instruction management, data collection processing and issuing. The main functions implemented in this module:
[0028] (1) Generate frequency resource occupation notification information. The function of this information is to generate occupancy information of the wireless ad hoc network frequency and sub-carrier resources according to the data service overhead of the ad hoc network node and the network frequency resource occupation. This information includes the number of sub-carriers occupied by the station, number, and frequency and time information, and is broadcast to other station nodes in the entire network through the management channel.
[0029] (2) Exchange information such as carrier-to-noise ratio and other information with the management channel and the ad hoc network station in the same network, and build the network topology and routing path table. The network topology and routing path table are notified to the data processing module for data routing processing, and the destination node of the transmission and the relay node that may need to pass through are determined.
[0030] (3) The network topology and routing path table data information is stored in the SDRAM storage module, which interacts with users through application software, and visually presents the node and network status to users in graphics and text.
[0031] (4) Read the user's configuration parameters, and adjust the configuration of other modules according to the user's configuration parameters to achieve local configuration and wireless remote control device user frequency.
[0032] The data processing module mainly realizes the background encapsulation of the IP data that needs to be transmitted. Through the background encapsulation, the internal header data of the wireless ad hoc network station is encapsulated before the original IP data, indicating the internal number of the target wireless ad hoc network station, and according to the routing path information provided by the central processing module, it is possible to perform number relay The station node number is written into the internal header, and the header also includes that the data needs to be modulated by QPSK or COFDM modulation and sent to the modulation module; the modulation module will complete the modulation processing of the data and use SMA radio frequency The interface form is sent to an external power amplifier for amplification, and then sent back to the frequency conversion module after being amplified, and radiated through the antenna after the transceiver switch is switched; when receiving the signal, the signal received by the antenna is sent to the frequency conversion module and down-converted to an intermediate frequency signal of 150MHz. Then sent to the demodulation module for subsequent corresponding processing. The memory unit in the FPGA processing chip stores high-speed data acquisition ADC programming data, COFDM modulation and demodulation algorithm encoding and decoding, communication protocol receiving and sending algorithms, baseband digital signal processing programming data, up-down conversion control instructions, and self-organizing network algorithms. Routing protocol; the central processing module calls the data processing module by sending a program call instruction to the data processing module to process the received information packets accordingly.
[0033] The integrated service interface management module includes a power management module and a configuration management module. The power management module supplies power to each module; the configuration management module provides an interactive interface for network administrators to query network configuration and modify network configuration;
[0034] As a preferred embodiment, the power management module is provided with a set of power adapter interfaces and a battery box. When there is an external power supply condition, the power adapter interface supplies power to each module, and when there is no external power supply condition, the battery supplies power to each module. This design enables the present invention to adapt to various indoor and outdoor environments, especially harsh communication environments such as emergency rescue and disaster relief.
[0035] Further, the integrated service interface management module is externally provided with an IP interface, and when it is necessary to access the ad hoc network through a wired connection, the IP interface is used to access the ad hoc network, and the integrated service interface management module converts IP datagrams into Ethernet frames. This design enables the present invention to access the ad hoc network through wireless, or connect to the Internet through an IP interface, as a Mesh route.
[0036] Preferably, the dynamic ad hoc network wireless communication device further includes a VOIP module, which adopts G.726 coding technology, and the VOIP module is respectively connected with the central processing module and the integrated service management module to establish the internal voice communication channel of the wireless ad hoc network.
[0037] The invention adopts the Ethernet IP communication design, and the standard Ethernet TCP/IP interface design is adopted between the modules and the external modules. It has the characteristics of high speed, convenience, high scalability, and strong accessibility. Its design principles are as follows figure 2 As shown, the RJ45 network port is used externally, and the Ethernet port is used internally. The integrated service interface management module realizes the conversion function of IP datagram and Ethernet frame.
[0038] The present invention adopts a low power consumption design, which is based on a "CPU+FPGA" architecture design, reasonably allocates resources, reduces processing burden, and reduces the total power consumption of processing modules. In addition, the designed transmit operating power is 100mW, and the power consumption is low. The switch control method is adopted in the design, and the hardware design diagram is as image 3 Shown. In the signal transmitting state, turning off the receiving channel can prevent the transmitted signal from leaking to the receiving channel and causing interference and channel blockage; when in the receiving state, the transmitting channel is closed, so that the quiescent current of the power amplifier is basically zero, which greatly reduces the power amplifier Power consumption.
[0039] The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications are also It should be regarded as the protection scope of the present invention.
