Formation method of semiconductor structure

Abstract

The invention relates to a formation method of a semiconductor structure. The formation method comprises that a substrate is provided; a first dielectric layer is formed at the surface of the substrate, a sacrifice layer is formed in the first dielectric layer, and the surface of the sacrifice layer is leveled with the surface of the first dielectric layer; parts of the sacrifice layer and first dielectric layer are etched till the surface of the substrate is exposed, a first through hole is formed in the first dielectric layer; the residual sacrifice layer is removed, and an extension opening is formed in the first dielectric layer and communicates with the first through hole; a first conductive plug is formed in the first through hole and the extension opening; and a first conductive layer is formed at the surfaces of the first conductive plug and the first dielectric layer. The formed semiconductor structure is stable in electrical property and higher in reliability.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] In the semiconductor manufacturing process, the back-end process (BEOL, Back-EndOfLine) is used to form a metal interconnection structure for realizing electrical interconnection between device structures after forming various device structures. The metal interconnection structure includes a conductive plug and an electrical interconnection line on top of the conductive plug. Among them, the conductive plug is often used for electrical interconnection between the upper and lower conductive layers, and the electrical interconnection line is used to form a circuit structure together with the semiconductor device. [0003] figure 1 and figure 2 is a structural schematic diagram of a metal interconnection structure, figure 2 Yes figure 1 The schematic diagram of the top view struc...

AI Technical Summary

Problems solved by technology

[0004] However, with the continuous advancement of semiconductor technology, the reduction of semiconductor process nodes and the improvement of integration have become a development trend. The feature size (CD, Critical Dimension) of semiconductor devices continues to shrink, and the device density continues to increase, making the formation of metal interconnection structures The process is also challenged, and it is easy to cause poor contact between the conductive plug and the interconnection line, resulting in a decrease in the reliability of the formed integrated circuit

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