Double-signal-output phase-locked amplifier having continuously adjustable phase difference
A lock-in amplifier and phase difference technology, which is applied in the direction of amplifiers, parametric amplifiers, amplifier types, etc., to achieve the effect of accurate measurement
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specific Embodiment approach 1
[0015] Specific implementation mode one: combine figure 1 and figure 2 Describe this embodiment mode, a kind of phase difference continuously adjustable dual-signal output lock-in amplifier described in this embodiment mode includes FPGA1, second-order analog signal low-pass filter 4, DDS7, No. 1 four-quadrant multiplier 8, two No. four-quadrant multiplier 9 and adder 10;
[0016] Two DC signals U generated by FPGA1 0 sinθ and U 0 cosθ and are sent to No. 1 four-quadrant multiplier 8 and No. 2 four-quadrant multiplier 9 respectively;
[0017] FPGA1 controls DDS7 to generate two AC signals U 1 cos(ωt) and U 1 sin(ωt), where U 1 cos(ωt) is sent to No. 1 four-quadrant multiplier 8, U 1 sin (ωt) is divided into two paths, one of which is sent to No. two four-quadrant multiplier 9, and the other is sent to the excitation electrode of the sensor as the first output signal of the lock-in amplifier;
[0018] The No. 1 four-quadrant multiplier 8 is used to multiply the two sig...
specific Embodiment approach 2
[0024] Specific implementation mode two: combination figure 1 Describe this embodiment, this embodiment is a further limitation of a dual-signal output lock-in amplifier with continuously adjustable phase difference described in Embodiment 1. In this embodiment, a digital proportional integral is embedded in the FPGA1 Feedback loop filter 2 and No. 2 digital proportional integral feedback loop filter 3;
[0025] The second-order analog signal low-pass filter 4 sends the amplitude U, frequency f and phase of the feedback signal Ucos (ωt) to FPGA1;
[0026] No. 1 digital proportional-integral feedback loop filter 2 is used to read the amplitude U of the feedback signal Ucos(ωt) and restore it to U 1 ;
[0027] The No. 2 digital proportional-integral feedback loop filter 3 is used to read the frequency f of the feedback signal Ucos(ωt) and restore it to ω / 2π.
specific Embodiment approach 3
[0028] Specific implementation mode three: combination figure 1Describe this embodiment. This embodiment is a further limitation of a dual-signal output lock-in amplifier with continuously adjustable phase difference described in Embodiment 2. In this embodiment, the second-order analog signal low-pass filter 4 includes No. 1 operational amplifier 5 and No. 2 operational amplifier 6;
[0029] The first operational amplifier 5 and the second operational amplifier 6 are used to extract the amplitude U and phase of the feedback signal Ucos(ωt), and then send the amplitude U and phase of the feedback signal Ucos(ωt) to FPGA1.
[0030] like figure 2 As shown, an analog coupling external force is loaded on the quartz tuning fork mechanical sensor 11 .
[0031] 1. Phase-locked control of quartz tuning fork mechanical sensor 11:
[0032] First, the Direct Digital Synthesizer (DDS) is controlled by the Field Programmable Gate Array (FPGA) to generate a set of AC signals U 1 sin(ωt...
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