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Formation method of semiconductor structure

A semiconductor and gate conductive layer technology, which is applied in the field of semiconductor structure formation, can solve the problems of the semiconductor structure production yield and chip output, etc., and achieves the effect of reducing the probability of peeling, simple type, and preventing adverse effects.

Active Publication Date: 2019-01-22
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the production yield and chip output of the prior art semiconductor structures still need to be improved

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Embodiment Construction

[0033] It can be seen from the background art that the substrate in the prior art device production process is easily damaged or polluted, resulting in low production yield of the semiconductor structure and low chip output.

[0034] It has been found through research that in semiconductor manufacturing, multiple processes need to be involved, and the dry etching process is usually a common step in the manufacturing process. The dry etching process uses the reactive gas to obtain energy, and then etches the etching object through a physical or chemical reaction. However, during etching, or other processes, by-products are usually formed near the edge of the substrate, such as polymers containing elements such as carbon, oxygen, nitrogen, and fluorine, and low-quality films due to edge effects layers etc.

[0035] In the subsequent process, the adhesion between the by-product and the substrate will eventually weaken, causing the by-product to spall or peel off during the trans...

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Abstract

The invention provides a method for forming a semiconductor structure. The method comprises following steps: providing a substrate and a first interlayer dielectric layer; etching and removing a first pseudo-grating and forming a first opening in the first interlayer dielectric layer of a first region; forming a first grating conducting layer which stuffs the first opening, and forming a first conductive adhering layer on the surface of the first interlayer dielectric layer of a peripheral region, wherein the material of the first conductive adhering layer is identical with that of the first grating conducting layer; performing first hypotenuse etching process, etching and removing the first conductive adhering layer and the first interlayer dielectric layer of the peripheral region to expose the peripheral region substrate surface; forming a second grating conducting layer in the first interlayer dielectric layer of a second region; forming a second interlayer dielectric layer covering the first interlayer dielectric layer, the first grating conducting layer, the second grating conducting layer, and the peripheral region substrate. Complex types of by-products are prevented from forming on the substrate of the peripheral region and therefore the chances that by-product may be peeled off from the substrate and fall on other substrates are prevented; the yield rate of semiconductor structures is increased.

Description

technical field [0001] The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the development of integrated circuits to ultra-large scale integrated circuits, the circuit density inside integrated circuits is increasing, and the number of components contained is also increasing. In a semiconductor integrated circuit, a Metal Oxide Semiconductor (MOS, Metal Oxide Semiconductor) transistor is one of the most important components. [0003] The existing MOS transistor process is to form a gate structure on a semiconductor substrate, form a source region and a drain region in the semiconductor substrate on opposite sides of the gate structure; then form contacts on the gate structure, source region and drain region The contact via is filled with metal in the contact hole to form a conductive plug, and the external circuit is electrically connected to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/28
Inventor 张海洋张城龙
Owner SEMICON MFG INT (SHANGHAI) CORP