Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Wiring board with embedded interposer integrated with stiffener and method of making the same

A manufacturing method and reinforcement layer technology, applied in printed circuit manufacturing, circuit, printed circuit, etc., can solve problems such as poor reliability of chip-level connections

Inactive Publication Date: 2016-07-20
BRIDGE SEMICON
View PDF9 Cites 6 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] To make matters worse, since the coefficient of thermal expansion of semiconductor chips (about 3 to 4ppm for silicon) is lower than that of organic substrates (about 15ppm for epoxy resin), it often causes interface stress due to mismatching coefficient of thermal expansion (CTE), making chip-level connections (chip-level connection) poor reliability

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Wiring board with embedded interposer integrated with stiffener and method of making the same
  • Wiring board with embedded interposer integrated with stiffener and method of making the same
  • Wiring board with embedded interposer integrated with stiffener and method of making the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0099] Figure 1-24 It is a diagram of a manufacturing method of a circuit board in the first embodiment of the present invention, which includes an interposer 11 , a positioning member 14 , a resin molded reinforcing layer 30 and a build-up circuit 40 .

[0100] figure 1 and 2 They are respectively a cross-sectional view and a bottom perspective view of the substrate 111 , which includes a first surface 101 , an opposite second surface 102 , and a blind hole 104 formed on the first surface 101 . The substrate 111 may be made of silicon, glass or ceramics, and has a thickness of 50 μm to 500 μm. The blind holes 104 have a depth of 25 microns to 250 microns. In this embodiment, the substrate 111 is a silicon wafer and has a thickness of 200 micrometers, and the blind hole 104 has a depth of 150 micrometers.

[0101] image 3 It is a cross-sectional view after forming the metallized via 116 . Metallized vias 116 are formed in the substrate 111 by depositing metal in the bl...

Embodiment 2

[0128] Figure 28-37 It is a diagram of a circuit board manufacturing method according to the second embodiment of the present invention, wherein the manufacturing method does not use a carrier film.

[0129] For the purpose of brief description, any descriptions in the above-mentioned embodiment 1 that can be used for the same application are incorporated here, and it is not necessary to repeat the same descriptions.

[0130] Figure 28 It is a sectional view of multiple sets of positioning elements 14 on the sacrificial carrier 13 . In this embodiment, after the positioning member 14 is formed on the sacrificial carrier 13, the sacrificial carrier 13 is then processed into a configuration having a plurality of protrusions 131 and a flange 133. This configuration can usually be It is formed by etching or mechanical carving (carving). Here, these bump parts 131 protrude from the flange part 133, and may have a protruding height of 0.1 to 1.0 mm, and the flange part 133 is l...

Embodiment 3

[0144] Figure 39-46 It is a diagram of the circuit board manufacturing method according to the third embodiment of the present invention, which includes the step of attaching the finished interposer to the sacrificial carrier.

[0145] For the purpose of brief description, any descriptions in the above embodiments that can be used for the same application are incorporated here, and the same descriptions do not need to be repeated.

[0146] Figure 39 and 40 They are respectively a cross-sectional view and a top perspective view of a positioning member 14 on the sacrificial carrier 13 . In this embodiment, the sacrificial carrier 13 is processed to have a configuration of a protruding portion 131 and a flange portion 133 , and then the positioning member 14 is formed on the protruding portion 131 of the sacrificial carrier 13 . Here, the protrusion portion 131 protrudes from the flange portion 133 , and the flange portion 133 extends laterally from the protrusion portion 13...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A wiring board with embedded interposer is characterized in that the embedded interposer is integrated with a stiffener and a build-up circuitry is deposited on the stiffener, so that the mechanical robustness of the stiffener can prevent the entire wiring board from warping. The interposer provides primary fan-out routing whereas the build-up circuitry provides further fan-out routing and can further enlarge the pad size and pitch of the interposer.

Description

technical field [0001] The invention relates to a circuit board, in particular to a circuit board with an intermediary layer embedded in a resin molded reinforcing layer and a manufacturing method thereof. Background technique [0002] For high-pin-count semiconductor chip packages and assemblies, it is necessary to provide a high-density circuit board for semiconductor chips to be connected to it, and then to wire the chip I / O pads with a larger pad pitch to achieve reliable Board-level assembly. For example, various coreless substrates disclosed in US Pat. Nos. 9,060,455, 9,089,041, 8,859,912 and 8,797,757 are for fan-out routing of chips. Compared with a substrate with a core layer, a substrate without a core layer has advantages such as lower parasitic resistance, lower inductance and capacitance. Most importantly, the interconnect density of core-less substrates is much higher than that of existing substrates with core layers, which is an important characteristic requ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H01L21/60H01L23/488H01L23/52H01L23/12H01L23/14H05K3/00H05K1/00
CPCH01L21/48H01L23/12H01L23/14H01L23/488H01L23/52H01L24/18H05K1/00H05K3/00H01L24/97H01L2224/16225H01L2924/0002H01L23/13H01L23/145H01L21/561H01L21/568H01L23/562H01L21/486H01L23/49827H01L23/49894H01L2224/16235H01L21/4846H01L21/4853H01L21/4875H01L23/49811H05K1/112H05K3/4007H05K3/4038
Inventor 林文强王家忠
Owner BRIDGE SEMICON
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com