Memory access method, storage-class memory and computer system

Abstract

The embodiment of the invention provides a memory access method, a storage-class memory and a computer system. The computer system comprises a memory controller and a hybrid memory, wherein the hybrid memory comprises a DRAM (dynamic random access memory) and the SCM (Storage-Class Memory); the memory controller is used for sending a first access instruction to the DRAM and the SCM; and when the SCM determines that a first memory cell set of the DRAM to which a first address points in the received first access instruction comprises a memory cell of which the retention time is shorter than the refresh cycle of the DRAM, a second address which has a mapping relationship with the first address can be obtained. Furthermore, the SCM transforms the first access instruction to a second access instruction for accessing the SCM according to the second address to realize the access of the SCM. The computer system provided by the embodiment of the invention can guarantee data correctness on the basis of the reduction of DRAM refresh power consumption.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a method for accessing memory, storage-level memory and a computer system. Background technique [0002] Traditional system main memory usually consists of dynamic random access memory (Dynamic Random Access Memory, DRAM). The structure of DRAM is simple and the reading speed is fast. The most basic storage unit of a DRAM is a DRAM cell, and each DRAM cell includes a transistor and a capacitor. DRAMcell uses the amount of electricity stored in the capacitor to represent 0 and 1. According to this method, one DRAM cell can store one bit. Due to the leakage phenomenon of the capacitor, if the charge in the capacitor is insufficient, the stored data will be wrong. Therefore, in practical applications, the capacitor needs to be charged periodically. Through the charging and discharging of the capacitor, the reading, writing and updating of the DRAM cell can be realized, which c...

AI Technical Summary

Problems solved by technology

However, if the DRAM refresh cycle is extended in order to reduce system power consumption, it may cause errors in the data in the memory

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