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A kind of conductive pad manufacturing method

A manufacturing method and a technology of conductive pads, which are applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve the problems of large semiconductor chip device size, large chip area, and affecting the electrical properties of the oxide layer, so as to reduce the area, The effect of narrowing the gap

Active Publication Date: 2018-09-28
FOUNDER MICROELECTRONICS INT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the contact hole area in the active area of ​​the oxide layer is equipotential, when the size of the PAD is almost the same as the contact hole area in the active area of ​​the oxide layer, the size of the semiconductor chip device will be larger
However, if the contact hole area in the active area of ​​the oxide layer is too small, since there is no dielectric layer between the oxide layer and the metal layer, the large-area field plate electric field of the metal layer will directly reach the surface of the oxide layer, thereby affecting the electrical properties of the oxide layer.
[0004] To sum up, the problem of large memory chip area in the prior art

Method used

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  • A kind of conductive pad manufacturing method
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  • A kind of conductive pad manufacturing method

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Experimental program
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Effect test

Embodiment 1

[0028] image 3 A process flow diagram of a PAD manufacturing method provided in an embodiment of the present invention, specifically including the following steps:

[0029] Step 101, etching the oxide layer on the first type conductive layer to form contact holes in the active region;

[0030] Step 102, etching the polysilicon layer formed on the oxide layer to form a gate;

[0031] Step 103, growing a dielectric layer on the gate and on the oxide layer;

[0032] Step 104 , forming a metal layer on the active region and on the dielectric layer to form a PAD; wherein, the distance between the contact holes in the active region is smaller than the side length of the PAD on the dielectric layer.

[0033] In step 101, an oxide layer is formed on the first type of conductive layer, and then a layer of photoresist is coated on the oxide layer according to the size of the contact hole in the active area, and then the photoresist is exposed through a mask to form a photoresist For...

Embodiment 2

[0043] As shown in the figure, this embodiment provides a single aluminum chip PAD manufacturing method, and its specific process is as follows Figure 4a to Figure 4d Shown:

[0044] Step 201, etching contact holes in the active region in the oxide layer on the first type conductive layer;

[0045] In the embodiment of the present invention, the first type of conductive layer may be an N-type epitaxial layer or a P-type epitaxial layer.

[0046] An oxide layer is grown on the first type of conductive layer, and a layer of photoresist is coated on the oxide layer according to the distance between the contact holes in the active area, and then the photoresist is exposed through a mask plate to form a photoresist mask, forming The photoresist mask is used to etch the oxide layer into required contact holes in the active region on the basis of forming the photoresist mask. The etching method in this embodiment includes but not limited to dry etching, wet etching, mixed use of d...

Embodiment 3

[0058] As shown in the present embodiment three, a kind of double aluminum chip PAD manufacturing method is provided, and its specific process is as follows Figure 5a to Figure 5f Shown:

[0059] Since the double aluminum chip PAD is made on the basis of the single aluminum chip PAD, so in the embodiment of the present invention Figure 5a to Figure 5c and in the second embodiment of the present invention Figure 4a to Figure 4c The production process is exactly the same. I won't repeat them here.

[0060] In this embodiment of the present invention, step 203 in Embodiment 2 follows.

[0061] In step 204-1, a metal layer is fabricated on the active region and the dielectric layer to form a PAD; wherein, when the metal layer is fabricated, the metal layer is fabricated in segments to form a PAD such as Figure 5d The metal layer shown, that is, PAD, includes Metal1 and M1 on both sides of Metal1, wherein the side length of Metal1 on the dielectric layer is greater than the...

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Abstract

The invention discloses a PAD making method. The PAD making method mainly comprises steps that an oxide layer on a first type conductive layer is etched to form active region contact holes; a poly-silicon layer formed on the oxide layer is etched to form a grid electrode; a dielectric layer respectively grows on the grid electrode and the oxide layer; a metal layer is respectively made on an active region and the dielectric layer, and the PAD is formed; gaps of the active region contact holes are smaller than an edge of the PAD on the dielectric layer. Through the method, an electric field barrier layer is introduced on the condition that not any process step is added, the gaps of the active region contact holes on the oxide layer of a PAD region are reduced, and thereby areas of chips are reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor chip manufacturing, in particular to a method for manufacturing a conductive pad PAD. Background technique [0002] With the rapid development of the semiconductor industry, the device size of the semiconductor chip is also shrinking day by day, but while the device size is getting smaller and smaller, the size of the connection area between the chip and the outside world, that is, the position of the conductive pad PAD, has always been relatively large. The PAD structure of the traditional chip I / O port is as follows: figure 1 and figure 2 shown, where figure 1 Shown is the PAD structure of a traditional single aluminum chip, figure 2 It is the PAD structure of the traditional double aluminum chip. In the figure, FOX is an oxide layer, ILD is the isolation dielectric layer between Metal1 and the oxide layer, and IMD is the isolation dielectric layer between Metal1 and Metal2. [0003]...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/48
Inventor 杜蕾
Owner FOUNDER MICROELECTRONICS INT