A trench oxide etching method for improving coupling rate of deep submicron flash memory devices

Abstract

The method of the present invention proposes a trench oxide etching method for improving the coupling rate of deep submicron-level flash memory devices, which adopts the combination of first dry etching + wet etching + second dry etching, and uses dry etching Effectively overcome the uneven density of filled oxides, remove the oxides in the loose-density area at the opening in the trench by the first dry etching, so that the oxide interface of the subsequent etching can maintain the same height and uniform density, and then The oxide sidewall of the sidewall of the polycrystalline floating gate caused by the first dry etching is removed by wet etching, so that this part of the sidewall is completely free of oxide coverage, and then the second dry etching is used to achieve a highly consistent trench The bottom of the oxide in the groove, and the oxide sidewall at the bottom of the sidewall of the polycrystalline floating gate that protects the tunnel oxide layer with uniform morphology, ONO deposition, forming a consistent ONO capacitance composed of ONO and polycrystalline floating gate contact, In this way, the coupling rate of the deep submicron-level flash memory device is improved, and the product qualification rate and service life are improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a trench oxide etching method for improving the coupling rate of deep submicron flash memory devices. Background technique [0002] With the continuous development of integrated circuit manufacturing process, the feature size of devices is also continuously reduced. The technology of submicron and deep submicron flash memory devices is becoming more and more mature. As an important structure for storing data in flash memory devices, polycrystalline floating gate transistors have been improved by the market. requirements are quite urgent. [0003] figure 1 It is the basic structure of a polycrystalline floating gate transistor as a basic storage unit (cell). [0004] As shown in the figure, each polycrystalline floating gate transistor is a three-terminal device, which are source 1, drain 2 and gate 3 respectively. The effect of the electric field is us...

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Problems solved by technology

[0018] The technical problem to be solved by the present invention is to reduce the difference in height of the bottom of the oxide in the trench, unify the oxide sidewall of the polycrystalline floating gate, and uniform the contact area between ONO and the sidewall of the polycrystalline floating gate, so as to realize the improvement of deep submicron flash memory The coupling rate of the device is the ultimate goal of improving the product qualification rate and service life

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