Glitch-type PUF circuit employing delay tree structure

A burr-type, tree-structured technology, applied in logic circuits, electrical components, pulse processing, etc., can solve problems that affect the practical progress of PUF circuits

Inactive Publication Date: 2016-09-07
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

With the increase of attack modes, it will serio

Method used

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  • Glitch-type PUF circuit employing delay tree structure
  • Glitch-type PUF circuit employing delay tree structure
  • Glitch-type PUF circuit employing delay tree structure

Examples

Experimental program
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Effect test

Embodiment 1

[0017] Embodiment one: if Figure 1-Figure 3 As shown, a glitch-type PUF circuit using a delay tree structure includes a timing control circuit, a shift register, a Glitch generation circuit with the same n-bit structure, a delay sampling circuit, an output circuit, and an n-input XOR gate XOR1, where n is an integer And 1≤n≤128; the delay sampling circuit includes a delay sampling unit with the same n-bit structure, the delay sampling unit includes a first inverter F1 and a D flip-flop D1, and the D flip-flop D1 has a clock terminal, an input terminal and an output terminal, The input end of the first inverter F1 is the input end of the delay sampling unit, the output end of the first inverter F1 is connected to the input end of the D flip-flop D1, and the output end of the D flip-flop D1 is the output end of the delay sampling unit , the clock terminal of the D flip-flop D1 is the clock terminal of the delay sampling unit, the clock terminal of the n-bit delay sampling unit ...

Embodiment 2

[0020] Embodiment two: if Figure 1-Figure 3 As shown, a glitch-type PUF circuit using a delay tree structure includes a timing control circuit, a shift register, a Glitch generation circuit with the same n-bit structure, a delay sampling circuit, an output circuit, and an n-input XOR gate XOR1, where n is an integer And 1≤n≤128; the delay sampling circuit includes a delay sampling unit with the same n-bit structure, the delay sampling unit includes a first inverter F1 and a D flip-flop D1, and the D flip-flop D1 has a clock terminal, an input terminal and an output terminal, The input end of the first inverter F1 is the input end of the delay sampling unit, the output end of the first inverter F1 is connected to the input end of the D flip-flop D1, and the output end of the D flip-flop D1 is the output end of the delay sampling unit , the clock terminal of the D flip-flop D1 is the clock terminal of the delay sampling unit, the clock terminal of the n-bit delay sampling unit ...

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PUM

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Abstract

The invention discloses a glitch-type PUF circuit employing delay tree structure, and the structure comprises a time sequence control circuit, a shift register, n delay tree circuits with the same bit structure, a delay sampling circuit, an output circuit, and n input XOR gates. The delay sampling circuit comprises n delay sampling units with the same structure, and each delay sampling unit comprises a first phase inverter and a D contactor. Each Glitch generation circuit consists of multi-stage '1' hazard circuits and '0' hazard circuits. The time sequence control circuit provides clock signal for the shift register, the delay sampling circuit and the output circuit. The time sequence control circuit enables control information to be stored in the shift register, and an input signal inputted to an n-bit Glitch generation circuit sequentially passes through each delay sampling unit of the delay sampling circuit. Each delay sampling unit decides the output data of the PUF circuit. The shift register enables the output data to be outputted to the output circuit, and to serve as the output data of the glitch-type PUF circuit. The circuit is advantageous in that the circuit is remarkable in nonlinear characteristics and can effectively solve a model attack problem.

Description

technical field [0001] The invention relates to a PUF circuit, in particular to a burr-type PUF circuit adopting a delay tree structure. Background technique [0002] In modern information security systems, Physical Unclonable Functions (Physical Unclonable Functions, PUF) circuits have been widely used as identity authentication and anti-counterfeiting means, such as smart cards, credit cards, electronic tags (Radio Frequency Identification Devices, RFID), mobile phones, security Video cameras and gaming equipment and more. The PUF circuit belongs to the chip feature recognition circuit, which is unique, random and unclonable. By extracting the unavoidable process deviation introduced in the chip manufacturing process, an infinite number of unique data information is generated. Applying PUF circuits to security devices can effectively defend against traditional attack modes, such as mathematical attacks, virus attacks, differential power consumption attacks, and collision ...

Claims

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Application Information

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IPC IPC(8): H03K19/0948H03K5/00
CPCH03K19/0948H03K5/00H03K2005/00241
Inventor 张跃军汪鹏君李刚钱浩宇
Owner NINGBO UNIV
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