Memristor circuit of realizing NAND gate or NOR gate logic and realization method thereof

Abstract

A memristor circuit of realizing NAND gate or NOR gate logic of the present invention comprises a memristor M1 and a memristor M2. The positive end of the memristor M1 is connected with the drain of an NMOS transistor N1 and the source of an NMOS transistor N2, the negative end of the memristor M1 is connected with the source of an NMOS transistor N5 and the drain of an NMOS transistor N6, and the source of the NMOS transistor N1 and the drain of the NMOS transistor N5 are connected as an input end V1. The positive end of the memristor M2 is connected with the source of an NMOS transistor N3 and the drain of an NMOS transistor N4, the negative end of the memristor M2 is connected with the drain of an NMOS transistor N7 and the source of an NMOS transistor N8, and the source of the NMOS transistor N4 and the drain of the NMOS transistor N8 are connected as an input end V2. The drain of the NMOS transistor N2, the drain of the NMOS transistor N3,the source of the NMOS transistor N6, the source of the NMOS transistor N7 and the input end V3 of a phase inverter are connected mutually, and the output end of the phase inverter is used as the output end Vout of the memristor circuit. The grids of the NMOS transistors N1, N4, N6 and N7 are connected with an A-selection end, and the grids of the NMOS transistors N2, N3, N5 and N8 are connected with a B-selection end. The present invention also relates to a realization method of the memristor circuit. According to the present invention, a new idea is provided for the parts capable of being played by the memristors in the logic operation.

Description

technical field [0001] The present invention relates to a memristor circuit for realizing NAND and NOR gate logic and its realization method. Background technique [0002] The AND (OR) NOT gate is a basic logic circuit in digital circuits. In a NAND gate, when both inputs are high (1), the output is low (0). When at least one of the inputs is low (0), the output is high; the NOR gate is just the opposite, and when the inputs are all low (0), the output is high. When the input has at least one high level (1), the output is low level (0); the AND (OR) NOT gate logic circuit is combined with other logic in the digital system to complete complex logic operation functions, such as using AND Not, NOR, and XOR are combined to complete a certain codec function, etc. The traditional AND (OR) NOT gate logic circuit is mainly composed of a plurality of MOS transistors and has a large area. At the same time, Moore's Law in the field of transistors is approaching its limit, it is dif...

AI Technical Summary

Problems solved by technology

The traditional AND (OR) gate logic circuit is mainly composed of multiple MOS transistors, with a large area

At the same time, Moore's Law in the field of transistors is approaching its limit, and it is difficult to reduce the size of MOS transistors. The area of ​​traditional CMOS logic circuits cannot continue to be reduced accordingly.

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