4 results about "Memristor circuits" patented technology

This invention discloses a memristor circuit based on a single field-effect transistor (FET) and four diodes, including an N-channel FET M0 and four diodes D0, D1, D2, and D3. The input is connected to the "D" terminal of M0, the "S" terminal of M0 is grounded, the "B" terminal of M0 is connected to the cathode of D2, and the "G" terminal of M0 is connected to the cathode of D0. The anodes of D0 and D1 are connected, and then connected to the anodes of D2 and the cathodes of D3. The cathodes of D1 and D3 are grounded.

This invention discloses a hybrid gated loop unit circuit based on memristors. The invention includes a memristor circuit, a weight mapping circuit, a hybrid gate circuit, a candidate activation state circuit, and an output circuit. The signal output terminal of the memristor circuit is connected to the signal input terminal of the weight mapping circuit. Relying on an in-memory computing architecture, it can directly complete the entire computation process of the hybrid gated loop unit and its variant models at the hardware level, eliminating the need for frequent data transfer and interaction. This fundamentally reduces the amount of data transmission, effectively breaking through the bottleneck limitations of data transmission in traditional architectures. It integrates the update gate and reset gate in traditional gated loop units into a single hybrid gate structure. Through the gate value output by the hybrid gate, the retention ratio of historical hidden information can be flexibly and dynamically adjusted, while precisely controlling the degree of fusion between new and historical information, making the information processing of the entire unit more efficient and dynamically adaptable.

The application discloses a four-dimensional chaotic circuit based on a fractional-order memristor, and comprises a fractional-order memristor equivalent circuit, a first fractional-order chaotic circuit, a second fractional-order chaotic circuit, a third fractional-order chaotic circuit and a fourth fractional-order chaotic circuit; the four fractional-order chaotic circuits generate corresponding four chaotic sequences respectively. The application combines the fractional-order memristor circuit with the fractional-order chaotic circuit, and the circuit can exhibit rich dynamic characteristics by adjusting the parameter value of the corresponding resistance, so that the application has higher security and adaptability in engineering applications such as chaotic system encryption.

This invention belongs to the technical field of biomimetic circuit design, and discloses a multi-scale cue fusion device and a multi-stimulus competition system based on memristors. The fusion device includes: a state generation module, which includes a volatile memristor, a positive correlation mapping circuit, and a state comparison circuit; a stimulus intensity processing module, which includes a memristor circuit, a subtraction circuit, and a stimulus comparison circuit; a context-related processing module, which includes a context gating circuit, a memristor, a context comparison circuit, a latch, and a shaping circuit; a state feedback module, which includes a state gating circuit; and a fusion module, which is used to perform weighted summation of voltages and output a fusion significance voltage. Based on the above design, it can more realistically reflect the biological process of processing multi-scale information, obtain the true perception of stimuli by the biological body under the comprehensive influence of multi-scale information, and provide biomimetic accuracy. Moreover, the introduction of memristors in this invention can improve the processing speed of the device.