14 results about "Memristor circuits" patented technology

The embodiment of the application discloses a kind of bridge artificial neuron unit composition's bionic hearing positioning system based on memristor circuit, it is related to neural morphic computing and artificial intelligence hardware field.In the present application: bridge artificial neuron unit includes the first memristor analog circuit connected with first capacitor and first load resistance, and the second memristor analog circuit connected with second capacitor and second load resistance, which are connected by first bridge capacitor, and coupled with external circuit by second bridge capacitor.The unit can simulate the pulse emission and refractory behavior of biological neuron.A plurality of the unit can be connected in series to build a one-way pulse propagation chain, forming a pulse propagation network.Based on the network, a coincidence detector can detect the small time difference of multiple input signals and be applied to a bionic hearing system to achieve sound source positioning.The present application has simple structure, high degree of modularity, and can realize high-reliability analog pulse propagation and high-precision coincidence detection.

The invention provides a memristive circuit for simulating age-related associative memory anti-interference difference, and belongs to the field of brain-like calculation and memristive circuits, and the memristive circuit comprises a pulse generation module which is used for superposing a synchronous pulse signal with an interference signal; the interference gating module comprises a variable resistor unit and a gating logic unit connected with the variable resistor unit; two ends of the memristor storage module are respectively connected with the sampling resistor and the ground; the control logic module is used for determining the number of pulses based on the synchronous pulse signal, determining an associative memory weight fluctuation value based on the number of pulses and the signal sampled by the sampling resistor, and adjusting the variable resistor unit based on the size relation between the associative memory weight fluctuation value and the associative memory weight fluctuation threshold value of the corresponding age mode so as to adjust the age of the corresponding age mode. And the size of the noise suppression coefficient and the LTD / LTP ratio of the memristive storage module are determined. The problems that irrelevant stimulation interference in a real scene is ignored, age-related anti-interference difference design is lacked and simulation accuracy is low can be solved.

The present invention relates to a system and method for memristor crossbar array neural network with defective synaptics repair. There is provided a memristor circuit including a primary memristor crossbar array, a redundant memristor crossbar array; and a connection switching circuit for switching inputs from the primary memristor crossbar array to the redundant memristor crossbar array when a defective synaptic is detected in the primary memristor crossbar array.

This invention discloses a memristor circuit based on a single field-effect transistor (FET) and four diodes, including an N-channel FET M0 and four diodes D0, D1, D2, and D3. The input is connected to the "D" terminal of M0, the "S" terminal of M0 is grounded, the "B" terminal of M0 is connected to the cathode of D2, and the "G" terminal of M0 is connected to the cathode of D0. The anodes of D0 and D1 are connected, and then connected to the anodes of D2 and the cathodes of D3. The cathodes of D1 and D3 are grounded.

This invention discloses a hybrid gated loop unit circuit based on memristors. The invention includes a memristor circuit, a weight mapping circuit, a hybrid gate circuit, a candidate activation state circuit, and an output circuit. The signal output terminal of the memristor circuit is connected to the signal input terminal of the weight mapping circuit. Relying on an in-memory computing architecture, it can directly complete the entire computation process of the hybrid gated loop unit and its variant models at the hardware level, eliminating the need for frequent data transfer and interaction. This fundamentally reduces the amount of data transmission, effectively breaking through the bottleneck limitations of data transmission in traditional architectures. It integrates the update gate and reset gate in traditional gated loop units into a single hybrid gate structure. Through the gate value output by the hybrid gate, the retention ratio of historical hidden information can be flexibly and dynamically adjusted, while precisely controlling the degree of fusion between new and historical information, making the information processing of the entire unit more efficient and dynamically adaptable.

This invention relates to the field of nonlinear circuit technology, and more particularly to a hyper-jerk circuit with ReLU and an encryption method, comprising a ReLU memristor circuit and a hyper-jerk circuit. By changing the initial values ​​of the ReLU memristor circuit and the hyper-jerk circuit, different periodic states, stable point states, divergent states, and chaotic states are generated, exhibiting super-multi-stability behavior. This invention enables the encryption sequence of the memristor chaotic system to have higher initial value sensitivity, stronger quasi-randomness, and continuous broadband power spectrum characteristics compared to traditional chaotic systems. Applying it to image encryption can effectively increase its key space and improve its anti-decryption capability.

This invention discloses an equivalent analog circuit for a six-winged Chua's junction-type locally active memristor. The invention includes a state variable generation circuit and a state-dependent Ohm's law circuit; specifically, it includes a two-input inverting summation circuit, a multi-input inverting summation circuit, a non-inverting integrator circuit, a multiplier circuit, and an Ohm's law circuit. The two-input inverting summation circuit limits the absolute value calculation, while the multi-input inverting summation circuit and the non-inverting integrator circuit obtain the negative value of the state variable. The negative value of the state variable obtained from the output of the non-inverting integrator circuit is input into one of the multiplier circuits, and then the summation and multiplication operations are performed through two multiplier circuits. The Ohm's law circuit acts as a voltage follower connected to an external voltage. Applying Ohm's law to the resistor yields the relationship between current and voltage with respect to the state variable x. This invention overcomes the cost limitations of highly complex memristor circuits and achieves functional integration and optimization.

A novel adjustable light-operated memristive circuit belongs to the technical field of circuit design and is specifically provided with a magnetic signal generating circuit, an index signal generating circuit and a signal processing circuit, the input end of the magnetic signal generating circuit is connected with input voltage, the magnetic signal generating circuit is connected with a photoresistor, and the photoresistor is connected with the index signal generating circuit. The output end of the magnetic signal generating circuit is connected with the input end of the signal processing circuit through the index signal generating circuit. The beneficial effects are that the photoresistor is connected to the magnetic signal generation circuit, so that the circuit model can maintain the resistance state during power failure, and the resistance value can be changed according to illumination during power-on. Besides, the input charge state is regulated and controlled through the photoresistor, and the circuit resistance can change along with the charge quantity, so that different memristor hysteresis loop models are simulated, and meanwhile, a hysteresis loop simulation curve can be finely adjusted. The model not only improves the simulation precision of the memristor model, but also provides a new thought for optimizing the performance of the memristor in practical application.

The invention discloses an array operation implementation system and method based on a memristor, and belongs to the technical field of integrated circuit chip design and storage and calculation integration. According to the technical scheme, the array operation implementation method based on the memristor comprises an improved memristor circuit structure, an MOS circuit is added on the basis of an original FEIX method, the input end of a Schmitt trigger is connected with a common node of the memristor, the output end of the Schmitt trigger is connected with an output memristor Z, an original output memristor Y serves as a load resistor, and the output memristor Y serves as a load resistor. The width-to-length ratio of the added MOS circuit is adjusted to adjust the center voltage of the overturning point and the voltage of the output end; noise interference is suppressed through the improved memristor circuit structure, complex arithmetic operation is realized by using the reconfigurable bidirectional Crossbar array, data handling overhead is reduced through modular design, and the method has the advantages of improving operation reliability, supporting complex arithmetic operation and optimizing operation efficiency.

The application discloses a four-dimensional chaotic circuit based on a fractional-order memristor, and comprises a fractional-order memristor equivalent circuit, a first fractional-order chaotic circuit, a second fractional-order chaotic circuit, a third fractional-order chaotic circuit and a fourth fractional-order chaotic circuit; the four fractional-order chaotic circuits generate corresponding four chaotic sequences respectively. The application combines the fractional-order memristor circuit with the fractional-order chaotic circuit, and the circuit can exhibit rich dynamic characteristics by adjusting the parameter value of the corresponding resistance, so that the application has higher security and adaptability in engineering applications such as chaotic system encryption.

The embodiment of the invention discloses a bridging artificial neuron unit based on a memristor circuit and a bionic auditory positioning system, and relates to the field of neuromorphic calculation and artificial intelligence hardware. A bridging artificial neuron unit comprises a first memristor analog circuit connected with a first capacitor and a first load resistor and a second memristor analog circuit connected with a second capacitor and a second load resistor, and the first memristor analog circuit and the second memristor analog circuit are connected through a first bridging capacitor and are coupled with an external circuit through a second bridging capacitor. The unit can simulate pulse distribution and non-stress behaviors of biological neurons. A plurality of units are connected in series to construct a one-way pulse propagation chain to form a pulse propagation network. The coincidence detector constructed based on the network can detect the tiny time difference of multiple paths of input signals, and is applied to a bionic auditory system to realize sound source positioning. The device is simple in structure, high in modularization degree and capable of achieving high-reliability analog pulse propagation and high-time-precision coincidence detection.

This invention belongs to the technical field of biomimetic circuit design, and discloses a multi-scale cue fusion device and a multi-stimulus competition system based on memristors. The fusion device includes: a state generation module, which includes a volatile memristor, a positive correlation mapping circuit, and a state comparison circuit; a stimulus intensity processing module, which includes a memristor circuit, a subtraction circuit, and a stimulus comparison circuit; a context-related processing module, which includes a context gating circuit, a memristor, a context comparison circuit, a latch, and a shaping circuit; a state feedback module, which includes a state gating circuit; and a fusion module, which is used to perform weighted summation of voltages and output a fusion significance voltage. Based on the above design, it can more realistically reflect the biological process of processing multi-scale information, obtain the true perception of stimuli by the biological body under the comprehensive influence of multi-scale information, and provide biomimetic accuracy. Moreover, the introduction of memristors in this invention can improve the processing speed of the device.

The invention discloses a voltage-controlled memristor circuit. The voltage-controlled memristor circuit comprises N-channel field effect transistors M0 and M2 and a P-channel field effect transistor M1. The input vi is connected with the D end of the M0, the S end of the M0 is grounded, the B end of the M0 is connected with the D end of the M1, and the G end of the M0 is connected with the D end of the M2. The G end of the M1 is connected with the B end of the M2, and the S end of the M1 is connected with the vc1. The G end of the M2 is connected with the B end of the M1, and the S end of the M2 is connected with the vc2.

The invention discloses a hierarchical comparator based on a memristor, and belongs to the field of memristor circuits. The layered comparator based on the memristor comprises a layered comparator without sign bits and a layered comparator with sign bits, wherein each of the layered comparators comprises a memristor parallel structure; the comparison process of the hierarchical comparator without sign bits comprises the following steps of: firstly, carrying out 1-bit comparison on input to obtain comparison results corresponding to greater, smaller and equal; integrating the 1bit comparison results in pairs to obtain a final comparison result; the comparison process of the hierarchical comparator with sign bits comprises the following steps: separately processing the sign bits and non-sign bits, comparing and integrating the non-sign bits according to the comparison process of the hierarchical comparator without sign bits, and finally integrating the sign bits and the comparison result without sign bits again.