26 results about "Memristor circuits" patented technology

The invention, which belongs to the technical field of circuit design, discloses a wide-area super-multistable memristor chaotic circuit system comprising a memristor, a capacitor and an inductor. An equivalent circuit of the chaotic circuit system comprises a memristor circuit, a resistance network, a voltage conveyor, an anti-phase proportioner, an anti-phase proportion adder, an anti-phase integrator, a multiplier, an external inductor and a capacitor. The voltage conveyor is used for conveying a voltage value to isolate current transmission; the anti-phase proportioner is used for realizing proportional operation of the output voltage and the input voltage and enabling the polarities of the output voltage and the input voltage to be opposite; the anti-phase proportion adder is used for realizing additive operation of a plurality of input voltages, so that the sum is used as an output voltage and is in an anti-phase state; the anti-phase integrator is used for realizing integral operation on an input voltage signal; and the multiplier is used for realizing product operation of two input signals.

The invention discloses a wind direction recognition device and method based on humidity-sensitive memristor neurons. The device comprises a humidity-sensitive memristor, an LIF circuit, an FPGA and a displayer. The humidity-sensitive memristor is arranged in the middle of the device, and a circle of purified water covers the periphery of the humidity-sensitive memristor; the LIF circuit is arranged at the bottom of the passing device and is connected with the humidity sensitive memristor through a wire; the FPGA is connected with the LIF circuits, the LIF circuits are respectively connected with the comparator, and output results of the LIF circuits are respectively transmitted to a pulse neural network in the FPGA through the comparator for wind direction identification; the display is used for outputting wind direction identification results. The wind direction identification is realized based on the characteristics of high sensitivity and low power consumption of the humidity sensitive memristor, so that the wind direction identification system has wide application prospects in the fields of smart cities, precision agriculture and the like, and the wind direction identification technology can be promoted to develop in a more intelligent and more efficient direction.

The invention belongs to the related technical field of bionic circuit design, and discloses a memristor-based multi-scale clue fusion device and a multi-stimulus competition system, and the fusion device comprises a state generation module which comprises a volatile memristor, a positive correlation mapping circuit and a state comparison circuit; the stimulation intensity processing module comprises a memristor circuit, a subtraction circuit and a stimulation comparison circuit; the situation correlation processing module comprises a situation gating circuit, a memristor, a situation comparison circuit, a latch and a shaping circuit; the state feedback module comprises a state gating circuit; and the fusion module is used for carrying out weighted summation on the voltage and outputting a fusion saliency voltage. Based on the above design, the processing process of the organism on the multi-scale information can be reflected more truly, the real perceptibility of the organism on stimulation under the comprehensive influence of the multi-scale information is obtained, and the bionic accuracy is provided. Moreover, the memristor is introduced, so that the processing speed of the device can be improved.

The embodiment of the application discloses a kind of bridge artificial neuron unit composition's bionic hearing positioning system based on memristor circuit, it is related to neural morphic computing and artificial intelligence hardware field.In the present application: bridge artificial neuron unit includes the first memristor analog circuit connected with first capacitor and first load resistance, and the second memristor analog circuit connected with second capacitor and second load resistance, which are connected by first bridge capacitor, and coupled with external circuit by second bridge capacitor.The unit can simulate the pulse emission and refractory behavior of biological neuron.A plurality of the unit can be connected in series to build a one-way pulse propagation chain, forming a pulse propagation network.Based on the network, a coincidence detector can detect the small time difference of multiple input signals and be applied to a bionic hearing system to achieve sound source positioning.The present application has simple structure, high degree of modularity, and can realize high-reliability analog pulse propagation and high-precision coincidence detection.

The invention provides a memristive circuit for simulating age-related associative memory anti-interference difference, and belongs to the field of brain-like calculation and memristive circuits, and the memristive circuit comprises a pulse generation module which is used for superposing a synchronous pulse signal with an interference signal; the interference gating module comprises a variable resistor unit and a gating logic unit connected with the variable resistor unit; two ends of the memristor storage module are respectively connected with the sampling resistor and the ground; the control logic module is used for determining the number of pulses based on the synchronous pulse signal, determining an associative memory weight fluctuation value based on the number of pulses and the signal sampled by the sampling resistor, and adjusting the variable resistor unit based on the size relation between the associative memory weight fluctuation value and the associative memory weight fluctuation threshold value of the corresponding age mode so as to adjust the age of the corresponding age mode. And the size of the noise suppression coefficient and the LTD / LTP ratio of the memristive storage module are determined. The problems that irrelevant stimulation interference in a real scene is ignored, age-related anti-interference difference design is lacked and simulation accuracy is low can be solved.

The present invention relates to a system and method for memristor crossbar array neural network with defective synaptics repair. There is provided a memristor circuit including a primary memristor crossbar array, a redundant memristor crossbar array; and a connection switching circuit for switching inputs from the primary memristor crossbar array to the redundant memristor crossbar array when a defective synaptic is detected in the primary memristor crossbar array.

This invention discloses a memristor circuit based on a single field-effect transistor (FET) and four diodes, including an N-channel FET M0 and four diodes D0, D1, D2, and D3. The input is connected to the "D" terminal of M0, the "S" terminal of M0 is grounded, the "B" terminal of M0 is connected to the cathode of D2, and the "G" terminal of M0 is connected to the cathode of D0. The anodes of D0 and D1 are connected, and then connected to the anodes of D2 and the cathodes of D3. The cathodes of D1 and D3 are grounded.

The invention discloses a memristor circuit-based chaotic mapping and analog circuit implementation method, which comprises the following steps of: firstly, constructing a memristor circuit based on a memristor, and discretizing a model by redefining variables to obtain a new three-dimensional chaotic mapping; the influence of parameters and initial values on chaotic mapping is analyzed by means of a kinetic analysis method. In a selected parameter range, the chaotic mapping shows a quasi-periodic state and a chaotic state, and a parameter beta, k and an initial value z0 can control a chaotic attractor to move along a zn axis. In addition, the chaotic mapping also has the phenomena of offset enhancement and extreme multistability, and complexity analysis shows that the maximum SE can reach 0.9, which shows that the chaotic mapping can generate a pseudo-random sequence with better performance. Finally, an analog circuit of the chaotic mapping is constructed on a PSIM platform, and a theoretical reference is provided for academic research and engineering application.

This invention discloses a hybrid gated loop unit circuit based on memristors. The invention includes a memristor circuit, a weight mapping circuit, a hybrid gate circuit, a candidate activation state circuit, and an output circuit. The signal output terminal of the memristor circuit is connected to the signal input terminal of the weight mapping circuit. Relying on an in-memory computing architecture, it can directly complete the entire computation process of the hybrid gated loop unit and its variant models at the hardware level, eliminating the need for frequent data transfer and interaction. This fundamentally reduces the amount of data transmission, effectively breaking through the bottleneck limitations of data transmission in traditional architectures. It integrates the update gate and reset gate in traditional gated loop units into a single hybrid gate structure. Through the gate value output by the hybrid gate, the retention ratio of historical hidden information can be flexibly and dynamically adjusted, while precisely controlling the degree of fusion between new and historical information, making the information processing of the entire unit more efficient and dynamically adaptable.

The invention provides a single-layer full-connection memory storage circuit and method based on a nanometer memristor array, and relates to the technical field of memristor memory circuits. The circuit comprises an information input circuit, an information memory circuit and an information storage circuit which are connected in sequence, the information memory circuit comprises a plurality of groups of digital-to-analog converters (DAC) and a memristive cross array which are connected with one another, and the memristive cross array comprises a plurality of memristors and a plurality of MOS tubes. The information storage circuit comprises a plurality of I-V conversion circuits which are connected with one another, an analog-to-digital converter (ADC) and a field programmable gate array (FPGA). According to the technical scheme, the problems that in the prior art, a memristor circuit is complex in design principle, not easy to implement and low in accuracy are solved.

The invention relates to the technical field of hyper-chaotic circuits, in particular to a hyper-chaotic model circuit based on memristor coupling and an image encryption method, and the hyper-chaotic model circuit comprises a first cosine memristor circuit, a second cosine memristor circuit, a first integrating circuit, a second integrating circuit and a memristor coupling circuit; wherein the first cosine memristor circuit is connected with the first integrating circuit, the second cosine memristor circuit is connected with the second integrating circuit, and the memristor coupling circuit is connected with the first integrating circuit and the second integrating circuit; by setting the coupling strength and the initial state value, heterogeneous and homogeneous offset attractors are generated. The problem that in the prior art, there is no chaotic system with heterogeneous and homogeneous extreme multi-stability at the same time is solved.

This invention relates to the field of nonlinear circuit technology, and more particularly to a hyper-jerk circuit with ReLU and an encryption method, comprising a ReLU memristor circuit and a hyper-jerk circuit. By changing the initial values ​​of the ReLU memristor circuit and the hyper-jerk circuit, different periodic states, stable point states, divergent states, and chaotic states are generated, exhibiting super-multi-stability behavior. This invention enables the encryption sequence of the memristor chaotic system to have higher initial value sensitivity, stronger quasi-randomness, and continuous broadband power spectrum characteristics compared to traditional chaotic systems. Applying it to image encryption can effectively increase its key space and improve its anti-decryption capability.

This invention discloses an equivalent analog circuit for a six-winged Chua's junction-type locally active memristor. The invention includes a state variable generation circuit and a state-dependent Ohm's law circuit; specifically, it includes a two-input inverting summation circuit, a multi-input inverting summation circuit, a non-inverting integrator circuit, a multiplier circuit, and an Ohm's law circuit. The two-input inverting summation circuit limits the absolute value calculation, while the multi-input inverting summation circuit and the non-inverting integrator circuit obtain the negative value of the state variable. The negative value of the state variable obtained from the output of the non-inverting integrator circuit is input into one of the multiplier circuits, and then the summation and multiplication operations are performed through two multiplier circuits. The Ohm's law circuit acts as a voltage follower connected to an external voltage. Applying Ohm's law to the resistor yields the relationship between current and voltage with respect to the state variable x. This invention overcomes the cost limitations of highly complex memristor circuits and achieves functional integration and optimization.

The invention discloses a chaotic circuit based on an absolute value memristor, and relates to the field of chaotic systems, and the chaotic circuit comprises a first phase inverter circuit which is used for carrying out the phase inversion operation of a first signal, and obtaining a sixth signal; the absolute value memristor circuit is used for performing absolute value operation on the fifth signal to obtain a third intermediate signal; the first branch circuit is used for calculating the first signal, the second signal and the fourth signal at the previous moment; the second branch is used for calculating the first signal, the third signal and the fourth signal at the previous moment; the third branch is used for calculating the first signal and the second signal at the previous moment; the fourth branch is used for calculating the first signal, the third intermediate signal and the second signal at the previous moment; the fifth branch is used for carrying out operation on a fifth signal and a sixth signal at the previous moment; according to the invention, the complexity of the chaotic circuit is reduced while the complexity of the chaotic signal of the chaotic circuit is improved.

A novel adjustable light-operated memristive circuit belongs to the technical field of circuit design and is specifically provided with a magnetic signal generating circuit, an index signal generating circuit and a signal processing circuit, the input end of the magnetic signal generating circuit is connected with input voltage, the magnetic signal generating circuit is connected with a photoresistor, and the photoresistor is connected with the index signal generating circuit. The output end of the magnetic signal generating circuit is connected with the input end of the signal processing circuit through the index signal generating circuit. The beneficial effects are that the photoresistor is connected to the magnetic signal generation circuit, so that the circuit model can maintain the resistance state during power failure, and the resistance value can be changed according to illumination during power-on. Besides, the input charge state is regulated and controlled through the photoresistor, and the circuit resistance can change along with the charge quantity, so that different memristor hysteresis loop models are simulated, and meanwhile, a hysteresis loop simulation curve can be finely adjusted. The model not only improves the simulation precision of the memristor model, but also provides a new thought for optimizing the performance of the memristor in practical application.

The invention discloses an array operation implementation system and method based on a memristor, and belongs to the technical field of integrated circuit chip design and storage and calculation integration. According to the technical scheme, the array operation implementation method based on the memristor comprises an improved memristor circuit structure, an MOS circuit is added on the basis of an original FEIX method, the input end of a Schmitt trigger is connected with a common node of the memristor, the output end of the Schmitt trigger is connected with an output memristor Z, an original output memristor Y serves as a load resistor, and the output memristor Y serves as a load resistor. The width-to-length ratio of the added MOS circuit is adjusted to adjust the center voltage of the overturning point and the voltage of the output end; noise interference is suppressed through the improved memristor circuit structure, complex arithmetic operation is realized by using the reconfigurable bidirectional Crossbar array, data handling overhead is reduced through modular design, and the method has the advantages of improving operation reliability, supporting complex arithmetic operation and optimizing operation efficiency.

The application discloses a four-dimensional chaotic circuit based on a fractional-order memristor, and comprises a fractional-order memristor equivalent circuit, a first fractional-order chaotic circuit, a second fractional-order chaotic circuit, a third fractional-order chaotic circuit and a fourth fractional-order chaotic circuit; the four fractional-order chaotic circuits generate corresponding four chaotic sequences respectively. The application combines the fractional-order memristor circuit with the fractional-order chaotic circuit, and the circuit can exhibit rich dynamic characteristics by adjusting the parameter value of the corresponding resistance, so that the application has higher security and adaptability in engineering applications such as chaotic system encryption.

The present invention provides a switchable floating - ground memristor emulator based on bidirectional symmetry characteristics, which includes three multipliers U1, U2, and U3, node z, capacitor C1, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, first switch S1, second switch S2, third switch S3, fourth switch S4, first voltage V1, second voltage V2, and two current - feedback operational amplifiers U4 and U5. The present invention is rooted in the memristor theory, derives the theoretical constraints that a floating - ground memristor with bidirectional conduction characteristics needs to satisfy, and gives a floating - ground memristor circuit that conforms to this structure, enabling the memristor emulator to have non - directionality, and the hysteresis loop is not affected by the connection direction. In addition, several switches are added to enable the circuit to freely switch between a grounded memristor and a floating - ground memristor, increasing the diversity of the circuit.

The present invention discloses a wind direction identification device and method based on humidity-sensitive memristor neurons. The device comprises: a humidity-sensitive memristor, a LIF circuit, an FPGA, and a display. The humidity-sensitive memristor is disposed in the middle of the device and is surrounded by a circle of pure water. The LIF circuit is disposed at the bottom of the device and is connected to the humidity-sensitive memristor via a wire. The FPGA is connected to each LIF circuit, each LIF circuit is connected to a comparator, and the output results of each LIF circuit are transmitted to a pulse neural network in the FPGA via the comparator for wind direction identification. The display is used to output the wind direction identification results. The present invention realizes wind direction identification based on the high sensitivity and low power consumption characteristics of the humidity-sensitive memristor, giving it broad application prospects in smart cities, precision agriculture, and other fields, and is conducive to promoting the development of wind direction identification technology towards a more intelligent and efficient direction.

The invention discloses a multi-butterfly-wing attractor chaotic circuit based on a memristive cell neural network, and the circuit comprises a cell neural network circuit N1 which generates basic chaotic signals and is provided with an i01 signal input end, an i02 signal input end, a negative x1 signal output end, a negative x1 signal output end, an x2 signal output end, a negative x2 signal output end, an x3 signal output end, and a negative x3 signal output end; the memristor circuit N2 is used for generating butterfly wing attractor signals and is provided with an x1 signal input end, a phi1 signal output end and an i01 signal output end; the memristor circuit N3 is used for generating butterfly wing attractor number control signals and is provided with a negative x1 signal input end, a phi 2 signal output end and an i02 signal output end. The circuit can generate any number of multi-butterfly-wing chaotic attractors, the randomness of chaotic signals is large, and the circuit can be used in the field of secret communication.

The embodiment of the invention discloses a bridging artificial neuron unit based on a memristor circuit and a bionic auditory positioning system, and relates to the field of neuromorphic calculation and artificial intelligence hardware. A bridging artificial neuron unit comprises a first memristor analog circuit connected with a first capacitor and a first load resistor and a second memristor analog circuit connected with a second capacitor and a second load resistor, and the first memristor analog circuit and the second memristor analog circuit are connected through a first bridging capacitor and are coupled with an external circuit through a second bridging capacitor. The unit can simulate pulse distribution and non-stress behaviors of biological neurons. A plurality of units are connected in series to construct a one-way pulse propagation chain to form a pulse propagation network. The coincidence detector constructed based on the network can detect the tiny time difference of multiple paths of input signals, and is applied to a bionic auditory system to realize sound source positioning. The device is simple in structure, high in modularization degree and capable of achieving high-reliability analog pulse propagation and high-time-precision coincidence detection.

This invention belongs to the technical field of biomimetic circuit design, and discloses a multi-scale cue fusion device and a multi-stimulus competition system based on memristors. The fusion device includes: a state generation module, which includes a volatile memristor, a positive correlation mapping circuit, and a state comparison circuit; a stimulus intensity processing module, which includes a memristor circuit, a subtraction circuit, and a stimulus comparison circuit; a context-related processing module, which includes a context gating circuit, a memristor, a context comparison circuit, a latch, and a shaping circuit; a state feedback module, which includes a state gating circuit; and a fusion module, which is used to perform weighted summation of voltages and output a fusion significance voltage. Based on the above design, it can more realistically reflect the biological process of processing multi-scale information, obtain the true perception of stimuli by the biological body under the comprehensive influence of multi-scale information, and provide biomimetic accuracy. Moreover, the introduction of memristors in this invention can improve the processing speed of the device.

The present invention discloses a multi-structure attractor chaotic circuit based on a memristive Hopfield neural network, comprising: a Hopfield neural network circuit N1 for generating a basic chaotic signal, and a memristor circuit N2 for generating a structure number control signal; the Hopfield neural network circuit N1 is provided with an x signal input terminal, an x1 signal output terminal, and a negative f(x1) signal output terminal, and the x1 signal output terminal is used for outputting a chaotic signal in the vertical direction; the memristor circuit N2 is provided with a #imgabs0# signal output terminal and an x signal output terminal, and its input terminal is connected to the negative f(x1) signal output terminal of the Hopfield neural network circuit N1, the x signal output terminal is connected to the signal input terminal of the Hopfield neural network circuit N1, and the #imgabs1# signal output terminal is used for outputting a chaotic signal in the horizontal direction; the circuit of the present invention can generate multi-structure chaotic attractors with any number (odd and even), the chaotic signal has large randomness, high encryption strength and strong anti-cracking ability. The invention can be used in the field of secure communication.

The invention discloses a voltage-controlled memristor circuit. The voltage-controlled memristor circuit comprises N-channel field effect transistors M0 and M2 and a P-channel field effect transistor M1. The input vi is connected with the D end of the M0, the S end of the M0 is grounded, the B end of the M0 is connected with the D end of the M1, and the G end of the M0 is connected with the D end of the M2. The G end of the M1 is connected with the B end of the M2, and the S end of the M1 is connected with the vc1. The G end of the M2 is connected with the B end of the M1, and the S end of the M2 is connected with the vc2.

The present invention discloses a wide-area super-multistable memristor chaotic circuit system, belonging to the field of circuit design technology. The chaotic circuit system is composed of a memristor, a capacitor, and an inductor. The equivalent circuit of the chaotic circuit system includes a memristor circuit, a resistor network, a voltage conveyor, an inverting proportional device, an inverting proportional adder, an inverting integrator, a multiplier, an external inductor, and a capacitor. The voltage conveyor is used to convey voltage values ​​and isolate current transmission; the inverting proportional device is used to perform a proportional operation between the output voltage and the input voltage and to make the polarity of the two opposite; the inverting proportional adder is used to perform an addition operation on multiple input voltages, so that the sum is used as the output voltage and is in antiphase; the inverting integrator is used to perform an integration operation on the input voltage signal; and the multiplier is used to perform a product operation on two input signals.

The invention discloses a hierarchical comparator based on a memristor, and belongs to the field of memristor circuits. The layered comparator based on the memristor comprises a layered comparator without sign bits and a layered comparator with sign bits, wherein each of the layered comparators comprises a memristor parallel structure; the comparison process of the hierarchical comparator without sign bits comprises the following steps of: firstly, carrying out 1-bit comparison on input to obtain comparison results corresponding to greater, smaller and equal; integrating the 1bit comparison results in pairs to obtain a final comparison result; the comparison process of the hierarchical comparator with sign bits comprises the following steps: separately processing the sign bits and non-sign bits, comparing and integrating the non-sign bits according to the comparison process of the hierarchical comparator without sign bits, and finally integrating the sign bits and the comparison result without sign bits again.