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A 10-bit high-precision DAC current source array and its layout method

A technology of current source array and layout method, used in electrical components, digital-to-analog converters, physical parameter compensation/prevention, etc., can solve problems such as systematic errors, poor matching of high and low current sources, and large random errors. , to achieve the effect of reducing chip area, accurate replication, and good monotonicity

Active Publication Date: 2019-06-07
南京德睿智芯电子科技有限公司
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Problems solved by technology

However, the existing 10-bit current source array layout has the problem of poor matching between high and low bit current sources, and the systematic error and random error are relatively large.

Method used

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  • A 10-bit high-precision DAC current source array and its layout method
  • A 10-bit high-precision DAC current source array and its layout method
  • A 10-bit high-precision DAC current source array and its layout method

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Embodiment Construction

[0032] The technical solutions provided by the present invention will be described in detail below in conjunction with specific examples. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0033] The 10-bit current steering DAC current source array requires a total of 1024 current source elements to form a 32*32 array. The present invention first generates a 16*16 sub-array Z waiting for rotation, mirroring, replacement, etc., and passes it through After multiple transformations, each 16*16 sub-array is obtained and combined into a final array according to a specific positional relationship. The present invention lays out an 8-bit high-precision DAC current source array through the following steps:

[0034] Step 1: Generate 16*16 (row*column) subarray Z.

[0035] Arrange the numbers 1-16 in a row from left to right in ascending order, then copy the...

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Abstract

The invention provides a 10-bit high-precision digital-to-analog converter (DAC) current source array and a layout method thereof. Firstly a mirror image to be rotated is generated for replacing a 16*16 sub-array Z to be converted, and the 16*16 sub-arrays are respectively obtained by multiple times of conversion and then are further composed into a final array. According to the layout method of the invention, matching of high and low current sources in the DAC current source array can be improved, integral non-linearity (INL) and differential non-linearity (DNL) characteristics of the DAC can be reduced, and a chip area is further reduced, and the space is saved; a current mirror can copy the current more accurately; and furthermore, a stray capacitance value can also be reduced, and surges generated during conversion between an MSB and an LSB can be effectively reduced. The layout of the same center of gravity adopted by the invention can be effectively improved, the influence of a ladder degree error can be counteracted, and mismatching of the current source array caused by systematic errors and random errors can be reduced while high conversion precision and high speed are ensured, so that the DAC circuit has better performance.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and relates to a layout technology of a current source array of a current steering digital-to-analog converter, in particular to a current source array and a layout method suitable for 10-bit DACs. Background technique [0002] DAC is Digital-to-Analog Converter. The research and application of this module mainly focus on the research of current source structure. With dynamic characteristics, it can be applied to electronic systems such as radar, communication, and electronic countermeasures that require high sensitivity. The mismatch of DAC includes random mismatch and systematic mismatch. The random error is mainly caused by some random factors, such as component size, doping, oxide layer thickness and other microscopic fluctuations that affect component parameters. Increase the component area to reduce the adverse effects of random mismatch on the circuit; system err...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/08H03M1/66
CPCH03M1/0845H03M1/662
Inventor 武鹏斌孙玉龙梁仁荣
Owner 南京德睿智芯电子科技有限公司
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