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Information system and method based on information pushing

A technology of an information processing system and an information processing method, which is applied in the computer field and can solve the problem that the memory access delay cannot be covered up.

Inactive Publication Date: 2016-11-23
SHANGHAI XINHAO MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

exist figure 2 In the information system, when the address 11 does not match the label in the label unit 14 of the LLC, the memory access delay is still unconcealed, and with the advancement of technology, this delay has increasingly become the bottleneck of computer performance improvement

Method used

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  • Information system and method based on information pushing
  • Information system and method based on information pushing
  • Information system and method based on information pushing

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0107] Please refer to image 3 , which is a schematic block diagram of the information processing system according to Embodiment 1 of the present invention. The address generator described in this embodiment is a dedicated computing unit, including several registers, and some or all of adders, shifters, and logic operators, at least capable of performing part of the functions of the processor, and can calculate Generate instruction or data address and make branch judgment. In this way, instructions related to memory address generation can be directly executed in the storage system, and the memory is accessed according to the calculated instruction or data memory address to read corresponding instructions or data and push them to the processor for execution.

[0108] exist image 3 In and in each embodiment described later, image 3 Processing systems below the dotted line with figure 1 Similar to the embodiment, 12 is a processor, and 12 may or may not include a buffer. ...

Embodiment 2

[0111] Please refer to Figure 4 , which is a schematic diagram of the frame structure of the information processing system in Embodiment 2 of the present invention, which is in image 3 On the basis of the embodiment, the same last-level cache LLC is added to both the processing system and the storage system. exist Figure 4 Among them, 10 in the storage system is a memory, 22 is an address generator, 24 is a label unit of the storage system LLC, 26 is a data memory RAM of the LLC in the storage system, and 28 is the output of the temporary storage address generator 22 to be stored in the memory 10 and the first-in-first-out (FIFO) of the data of LLC RAM 26, 18 is the selector that selects the storage data from 28 or processor 12 for storing into memory 10; The processing system under the dotted line and figure 2 Similar to the embodiment, 12 is a processor, 14 is a tag unit of the processing system LLC, and 16 is a data memory RAM of the processing system LLC. In the sto...

Embodiment 3

[0120] Please refer to Figure 6 , which is a schematic diagram of the frame structure of the information system in Embodiment 3 of the present invention, which is in Figure 4 Based on the embodiment, the LLC RAM 26 in the storage system is omitted, and the rest are the same. exist Figure 6 Among them, in the storage system on the dotted line, 10 is the memory, 22 is the address generator, 24 is the tag unit of the storage system LLC, 28 is the first-in-first-out (FIFO) output by the temporary storage address generator 22, and 18 is the selection from 28 or The selector for storing data of the processor 12; in the processing system under the dotted line, 12 is the processor, 14 is the label unit of the processing system LLC, and 16 is the data memory RAM of the processing system LLC. The instruction or data input to the address generator 22 comes directly from the output bus 23 of the memory 10 . The memory address output by the address generator 22 through the bus 21 add...

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PUM

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Abstract

The invention provides an information processing system and method. A storage address is generated by an independent address generator for having access to a storage, information is read to be executed by a processor, and the time when the processor waits for the information is shortened.

Description

technical field [0001] The invention relates to the fields of computer, communication and integrated circuit. In particular, it relates to an information processing system, an information processing method and a storage system. Background technique [0002] The processor in a stored-program computer reads instructions or data from the memory for execution by the CPU, and the results of the execution are sent back to the memory for storage. figure 1 It is a simplified block diagram of an existing stored program computer, wherein the processor 12 includes an execution unit and a control unit, 12 generates an address to access the memory 10 through the bus 11, and 10 provides information to 02 through the bus 13 according to the address on 11, here and The information described below includes computer instructions and data. The execution result data of the processor 12 is also stored back to 10 via the bus 13 . figure 1 Above the dotted line is the memory and its associated ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16G06F12/02
Inventor 林正浩
Owner SHANGHAI XINHAO MICROELECTRONICS