Embedded PIP capacitor CMOS manufacturing method

Abstract

The invention provides an embedded PIP capacitor CMOS manufacturing method. The method comprises the steps that a well region is formed in the surface of a substrate and an active region in the well region is defined, and a field oxide layer is formed on the surface of the substrate apart from the active region; a first polysilicon layer is formed on the surface of the partial region of the field oxide layer close to the periphery, and a mat oxide layer on the surface of the active region is removed; a dielectric layer is formed on the surface of the whole device; threshold ions are injected so that an injection region in the surface of the substrate corresponding to the active region is formed; the dielectric layer is etched and the dielectric layer on the first polysilicon layer is reserved; a gate oxide layer is formed on the surface of the substrate corresponding to the active region, and a second polysilicon layer is formed on the surface of the partial region of the dielectric layer and the gate oxide layer; and side walls enclosing the first polysilicon layer and enclosing the second polysilicon layer are formed on the surface of the substrate, and a source region, a drain region and a lightly doped drain region LDD of the device are formed. The influence of the conventional technology on the threshold ion distribution can be avoided and the performance of the device can be enhanced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a CMOS manufacturing method for embedding PIP capacitors. Background technique [0002] Polysilicon-dielectric layer-polysilicon (Polysilicon-Insulator-Polysilicon, referred to as PIP) capacitor is a structure, with a layer of polysilicon as the lower plate, another layer of polysilicon as the upper plate, and a thinner oxide layer in the middle is the capacitance of the dielectric layer. In the existing technology, PIP capacitors are usually embedded in complementary metal oxide semiconductor devices (Complementary Metal Oxide Semiconductor, referred to as CMOS), which are used for frequency modulation and to prevent noise emission from analog circuits. [0003] In the CMOS manufacturing process of embedded PIP, the traditional method is to grow an oxide layer as the dielectric layer of the PIP capacitor after etching the gate polysilicon, and then deposit a layer of ...

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Problems solved by technology

[0010] The disadvantage of the traditional PIP-embedded CMOS manufacturing process is that during the thermal process of growing the dielectric layer and depositing the second layer of polysilicon, the distribution of the implanted threshold ions will be affected, resulting in the CMOS device parameters and standard embedded PIP capacitance There are differences between CMOS device parameters without PIP capacitors, which affect device performance

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