A vertical nanowire device with sheath channel structure and its preparation method

Abstract

The invention discloses a vertical nanowire device with a sheath channel structure and a preparation method of the vertical nanowire device. A through hole is etched, a channel material is deposited, and silicon dioxide is filled to obtain the vertical nanowire device integrated with the sheath channel structure. The preparation method comprises the following steps: providing a semiconductor substrate to isolate devices; forming a heavily doped lower active region; depositing a pseudo gate stack; forming the sheath channel structure by etching the through hole, depositing the channel material and filling the silicon dioxide; forming a heavily doped upper active region by depositing and etching; removing pseudo gates, depositing HK and MG and forming a gate electrode; enabling metals of various ends of the formed devices to be in contact with one another; and integrating the devices according to an existing rear end process. Short channel effect control capability of the devices can be improved effectively, and leakage current is reduced; thicknesses, sectional area sizes and morphologies of channels of the devices can be controlled accurately, and the properties of the devices are improved by a rear gate process.

Description

technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuit manufacturing, and relates to a vertical nanowire device with a sheath channel structure and a preparation method thereof. The method combines etching through holes, depositing channel materials, and filling silicon dioxide to realize Vertical nanowire device integration of sheathed channel structures. Background technique [0002] When semiconductor devices enter the 22nm technology generation, the horizontal channel three-dimensional multi-gate device (Multi-gate MOSFET, MuGFET) represented by the fin field effect transistor (FinFET), with its outstanding ability to suppress the short channel effect, high integration density , Compatible with traditional CMOS technology and other advantages, it has become the mainstream of semiconductor devices. However, when moving towards smaller technology nodes, horizontal channel three-dimensional multi-gate devices face challe...

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Problems solved by technology

[0005] (1) If the diameter of the vertical channel is large, there will be a leakage path in the center of the channel away from the gate control area, which increases the power consumption of the device; but if you want to form a vertical channel with a smaller diameter and a large aspect ratio by etching The channel itself poses a great challenge to the etching process, and the cross-sectional morphology of the channel formed by etching is difficult to control, resulting in the degradation of the consistency of device characteristics, and the channel damage caused by etching, causing further degradation of device performance;

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