Low-voltage-difference linear voltage stabilizer

Abstract

The invention discloses a low-voltage-difference linear voltage stabilizer. The voltage stabilizer comprises an error amplifier (10), a voltage follower (20), an output circuit (30) and a compensation circuit (40). The output end of the error amplifier (10) has the high impedance characteristic, a pole p1 is formed at the output end, the output end of the error amplifier (10) is connected with the input end of the voltage follower (20), parasitic capacitance of the output end of the error amplifier is reduced, so the formed pole is far away from the original point, and the pole p1 is compensated for through a first compensation unit; besides, the compensation circuit (40) compensates a pole p2 formed by the grid electrode of a compensation power tube MP301, stability of loops in a full-load range is guaranteed in the compensation mode, accordingly influences of the pole of the error amplifier on the PSRR are eliminated, and characteristics of the PSRR are improved. An LDO circuit effectively expands the bandwidth of the loops, transient characteristics are improved, and a circuit implementation mode is simple.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a low-dropout linear regulator. Background technique [0002] Low-dropout linear regulator (LDO, Low-dropout Regulator) has the advantages of low output noise, simple circuit structure, small occupied chip area and small voltage ripple, and is an important part of the power management circuit. LDO can provide power supply with low output ripple, better power supply rejection ratio (PSRR, Power Supply Rejection Ration) and lower noise performance for noise-sensitive circuits such as analog circuits and radio frequency circuits, so it is widely used in handheld devices and in portable electronic products. [0003] With the rapid development of integrated circuits, the operating frequency of the chip continues to increase, and the PSRR performance of the LDO also decreases. The power supply noise affects the performance of the entire system through the LDO, ...

AI Technical Summary

Problems solved by technology

[0003] With the rapid development of integrated circuits, the operating frequency of the chip continues to increase, and the PSRR performance of the LDO also decreases. The power supply noise affects the performance of the entire system through the LDO, causing the system to fail to meet the application requirements of high-frequency working environments.

For example, in an LDO cascaded with a switching power supply, if the high-frequency PSRR characteristics of the subsequent LDO are not high, it will cause the high-frequency output ripple voltage of the switching power supply to be transmitted to the LDO output stage, thereby affecting the performance of the LDO load circuit, such as Noise-sensitive modules such as digital-to-analog conversion and radio frequency weaken or even deteriorate system performance

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