Secondary part parallel input right shift accumulation LDPC encoder

Abstract

The invention provides a QC-LDPC encoder based on a secondary assembly line. The encoder comprises a multiplier of a sparse matrix and a vector and a multiplier of a vector and a high density matrix. The multiplier of the sparse matrix and the vector realizes multiplication of the sparse matrix and the vector. The multiplier of the vector and the high density matrix uses a part parallel input right shift accumulation mechanism to realize multiplication of the vector and the high density matrix. The whole coding process is divided into two levels of assembly line. The QC-LDPC encoder provided by the invention has the advantages of low cost, high throughput and the like.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a QC-LDPC coder with two-stage partial parallel input right-shifting and accumulating in a communication system. Background technique [0002] Low-Density Parity-Check (Low-Density Parity-Check, LDPC) code is one of efficient channel coding techniques, and Quasi-Cyclic LDPC (QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of circulant matrices, which have the characteristics of a segmented cycle, so they are called QC-LDPC codes. The first row of the circulant matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of a circulant matrix is ​​called its generator polynomial. [0003] The c...

AI Technical Summary

Problems solved by technology

This scheme has two disadvantages: one is that a large amount of memory is required, resulting in high circuit cost; the other is that the information bits are serially input, and the encoding speed is slow

Images