On-chip bus test system based on Tbus bus standard

An on-chip bus, test system technology, used in faulty hardware testing methods, error detection/correction, detection of faulty computer hardware, etc.

Active Publication Date: 2017-06-13
CHENGDU FOURIER ELECTRONICS TECH +1
View PDF7 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, in the current application field of hardware board testing,...

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • On-chip bus test system based on Tbus bus standard
  • On-chip bus test system based on Tbus bus standard
  • On-chip bus test system based on Tbus bus standard

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0093] A typical embedded system includes FPGA chip, DSP chip and various peripheral interface chips. FPGA and DSP are connected by external bus EMIF. FPGA has external SRIO interface, UART bus interface, SPI bus interface and LVDS interconnection line. Using the traditional method to test the external interface of FPGA, it is necessary to write SRIO test program, LVDS test program, UART test program and SPI test program respectively. Various test programs may be individual test programs, or they may be integrated into one test program. However, each module of DSP operation does not have a unified underlying driver interface, and the driver is customized for each module, which is highly dependent on the platform. If the DSP is replaced by PPC, in addition to the modification of the driver program, the test module in the FPGA will also be modified accordingly, and the test process and result display will also have some changes.

[0094] Use the Tbus bus standard to design each ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to an on-chip bus test system based on the Tbus bus standard. The system includes a main control unit and a slave terminal device end which are communicated with each other through data flow; a device internetwork is arranged between the main control unit and the slave terminal device end; a signal group set of the main control unit includes a data output signal group Out, a data injection signal group Inject, a parameter control signal group Param, a state signal group Status and a control signal group Control; a signal group set of the slave terminal device end includes a data output signal group Out, a data injection signal group Inject, a parameter control signal group Param, a state signal group Status and a control signal group Control. All test peripheral units are connected with a test bus in a hung mode to form the test system, a unified and rapid operation method is used for operating each test peripheral unit, the integration of the test system is accelerated, test defects are reduced, and the testing efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of computer communication applications, in particular to an on-chip bus test system based on the Tbus bus standard. Background technique [0002] The on-chip bus, as the name implies, is the bus on the chip. Many buses can be considered as on-chip buses, such as the address bus and data bus in the single-chip microcomputer chip, and the custom bus inside the programmable logic chip, all of which can be called on-chip buses. On-chip buses are generally easier to implement parallel multi-bit transfers than off-chip buses. [0003] Nowadays, the on-chip bus is widely used in various processor chips, such as the AMBA bus specification adopted by the well-known ARM core chip, which is used to connect the processor core and various peripherals. The AMBA standard 2.0 specification defines three sets of bus protocols: AHB (High Performance Bus), ASB (System Bus) and APB (Peripheral Bus). Each bus interface plays a...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F11/22G06F11/273
CPCG06F11/221G06F11/2273G06F11/273
Inventor 操飞孙海飙林峰阴陶戴荣
Owner CHENGDU FOURIER ELECTRONICS TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap