Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Chip verification method, device and system

A verification method and chip technology, applied in the field of communication, can solve the problems of lack of hierarchy in verification architecture and low platform reusability, and achieve the effect of improving reusability and verification efficiency.

Active Publication Date: 2017-07-11
ZTE CORP
View PDF12 Cites 22 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The present invention provides a chip verification method, device and system to at least solve the problem of low reusability of the platform due to the lack of hierarchy of UVM verification architecture

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Chip verification method, device and system
  • Chip verification method, device and system
  • Chip verification method, device and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030] Hereinafter, the present invention will be described in detail with reference to the drawings and examples. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0031] It should be noted that the terms "first" and "second" in the description and claims of the present invention and the above drawings are used to distinguish similar objects, but not necessarily used to describe a specific sequence or sequence.

[0032] In this embodiment, a chip verification method is provided, figure 2 is a flowchart of a chip verification method according to an embodiment of the present invention, such as figure 2 As shown, the process includes the following steps:

[0033] Step S202, generating a verification platform, wherein the verification platform includes: a model layer and an interface layer, the model layer includes a traffic model and a register model, and the ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a chip verification method, device and system. The method comprises the following steps of: generating a verification platform, wherein the verification platform comprises a model layer and an interface layer, the model layer comprises a traffic model and a register model, and the interface layer comprises a data bus interface agent and a CPU bus interface agent; verifying a chip to be tested by using the verification platform. The chip verification method, device and system solve low reusability of the platform caused by lack of hierarchy of the verification architecture of the UVM, improve the reusability of the verification architecture, and improve verification efficiency.

Description

technical field [0001] The present invention relates to the communication field, in particular to a chip verification method, device and system. Background technique [0002] Logic verification is a key step in the front-end design process of digital chips. It verifies the actual operating environment of the platform simulation chip and verifies the correctness of the chip functions through test cases. With the rapid growth of digital integrated circuits in scale and complexity, and the rapid release of a large number of similar-function chips, higher requirements are placed on verification platforms and test methods in terms of time and cost. [0003] The traditional verification platform is the verification of the signal level, and the chip under test is verified by directly writing the test stimulus. The traditional verification platform lacks an abstract division of labor for platform functions, and there is no unified writing standard and application interface, resulti...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/317G01R31/3177
CPCG01R31/31718G01R31/3177G06F30/00
Inventor 朱仁霖
Owner ZTE CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com