Clock signal source with low phase noise and adjustable duty cycle

Abstract

The invention discloses a clock signal source with low phase noise and adjustable duty cycle. The clock signal source comprises an instruction generation unit, a communication processing unit, a central control unit, a digital-to-analog converter, a phase-locked loop, a clock oscillator, a transformer and a high-speed comparator, wherein the instruction generation unit is used for generating a control signal instruction that controls the output clock duty cycle and frequency; the communication processing unit is used for encoding the control signal instruction to generate a control signal bit stream; the central control unit is used for analyzing the specific meaning of the control signal bit stream and generating a corresponding first control bit stream and a second control bitstream; the digital-to-analog converter is used for receiving the first control bit stream and obtaining a first control signal; the phase-locked loop is used for receiving the second control bit stream and generating a differential clock output with adjustable frequency; the clock oscillator is used for providing a low-noise reference frequency source for the phase-locked loop; the transformer is used for converting the differential clock output to a single-end clock output to obtain a second control signal; and the high-speed comparator is used for receiving the first control signal and the second control signal and controlling the clock output unit to output a low-noise clock signal with the set frequency and duty cycle. By adopting the clock signal source disclosed by the invention, the cost of a test system of the digital-to-analog converter can be reduced.

Description

technical field [0001] The invention relates to a clock signal source with low phase noise and adjustable duty ratio, in particular to a clock signal source used in the testing field of high-speed and high-precision analog-to-digital converters. Background technique [0002] With the rapid development of the information technology industry, the application range of analog-to-digital converters is becoming wider and wider, and the performance requirements of analog-to-digital converters are getting higher and higher. The sampling clock is the basic element of the ADC. For the tester or application of the ADC, the clock scheme, clock type, clock voltage level, and clock jitter used by the ADC are very important. The jitter of the sampling clock is a short-term, non-accumulative variable, which represents the time deviation between the actual timing position of the digital signal and its ideal position. Clock jitter will cause the internal circuit of the analog-to-digital conv...

AI Technical Summary

Problems solved by technology

Traditional clock signal sources cannot effectively guarantee that the above two parameters meet the requirements at the same time. Some clock signal sources meet the phase noise requirements, but can only provide a clock signal with a fixed duty cycle of 50%; The ratio is adjustable, but the output clock phase noise does not meet the requirements

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