Direct solution technology-based VLSI standard unit layout method

Abstract

The invention relates to a direct solution technology-based VLSL standard unit layout method, and belongs to the technical field of VLSI physical design automation. According to the method, global VLSI standard unit layout problems are solved through establishing global density functions of the problems, carrying out convolutional smoothing by utilizing Gaussian functions and combining a wire length model. The key points of the technical scheme are as follows: (1) being different from the manner of obtaining discrete density function values by using a uniform bin division method, the method can more correctly depict the distribution condition, on a layout area, of units through a global density expression constrained by a calculation unit and the whole layout area in an overlapping area; (2) through considering that the discretion of the units is related to the densities of the places where the units are located and the densities of the surrounding places, the model carries convolutional smoothing on the global density functions by using the Gaussian functions, a penalty function method is adopted convert the wire length target and density constraint of VLSI global layout into unconstrained nonlinear planning problems, and a proper optimization technology is selected to carry out optimization.

Description

technical field [0001] The invention relates to the technical field of VLSI physical design automation, in particular to a VLSI standard cell layout method based on direct solution technology. Background technique [0002] In the current VLSI layout, the scale of integrated circuits continues to increase and the requirements for technology are getting higher and higher, which puts forward higher requirements for the optimization goals and optimization methods of VLSI layout, and the quality of the layout results directly affects the quality of the entire chip. performance. With the rapid growth of the number of units on a chip, especially the widespread application of millions of gate chips, it poses a huge challenge to the automation of VLSI layout design. Therefore, it is of great significance to seek more efficient and practical integrated circuit layout algorithms [0003] Algorithms used to solve VLSI placement problems can be divided into the following three categori...

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Problems solved by technology

[0005] However, the existing global layout methods based on analytical methods have the following two problems: (1) In the process of global layout, the method of uniformly dividing the layout area into bins is used for approximate calculation of density, because the density function is non-smooth , a smoothing approximation is also required

Therefore, there is a large error between the density constraint calculated after approximation and the actual density distribution, which is not a good reflection of the actual density of the layout, so that the quality of the layout cannot be guaranteed; (2) The existing layout tools have compared the layout problem to static electricity. field model method, but the indirect solution also has a certain impact on the quality of the solution

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