clock recovery device

Abstract

A clock recovery apparatus, comprising: an analog-to-digital converter (ADC) (21), a data buffer (22), a digital interpolator (23), a clock phase error estimator (24), a filter (20), and a digital controller (25). Output terminals of the ADC (21) are respectively connected to an input terminal of the data buffer (22) and a first input terminal (26) of the clock phase error estimator (24); the output terminal of the data buffer (22) is connected to a first input terminal (28) of the digital interpolator (23); the output terminal of the digital interpolator (23) is connected to a second input terminal (27) of the clock phase error estimator (24); the output terminal of the clock phase error estimator (24) is connected to the input terminal of the digital controller (25); the output terminal of the digital controller (25) is connected to a second input terminal (29) of the digital interpolator (23). The present invention reduces complexity of circuit design and facilitates the realization of a hardware circuit.

Description

technical field [0001] Embodiments of the present invention relate to communication technologies, and in particular to a clock recovery device. Background technique [0002] In an optical communication system, after the receiving end performs photoelectric conversion, it needs to perform algorithm processing in the digital domain. The rate at which the receiving end performs algorithm processing and the rate at which the transmitting end sends data must be consistent at all times to ensure that all transmitted data is timely. is processed, that is, the transmitter and receiver must ensure clock synchronization. If the clocks of the transmitting end and the receiving end deviate, the clock needs to be recovered to ensure that the sampling data at the receiving end is the sampling data at the best sampling time, so that the data at the receiving end and the transmitting end are kept in sync. [0003] figure 1 It is a structural schematic diagram of a clock recovery device in...

AI Technical Summary

Problems solved by technology

[0004] However, because the clock recovery device in the prior art not only recovers the clock signal with errors, but also needs to design devices such as VCO and LPF in the feedback loop to adjust the sampling clock of the ADC, the circuit design is complicated and not Conducive to the realization of hardware circuit

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