clock recovery device

A technology of clock recovery and clock phase, which is applied in the field of communication, can solve problems such as complex circuit design and unfavorable hardware circuit implementation, and achieve the effect of simplifying complexity and facilitating implementation

Active Publication Date: 2020-02-14
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, because the clock recovery device in the prior art not only recovers the clock signal with errors, but also needs to design devices such as VCO

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Example Embodiment

[0089] In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of the embodiments of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0090] figure 2 It is a schematic structural diagram of a clock recovery apparatus provided by Embodiment 1 of the present invention. Such as figure 2 As shown, the device includes an ADC 21, a data buffer 22, a digital interpolator 23, a clock phase error estimator 24, and a digital controller 25.

[0091] Among them, the output ter...

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Abstract

A clock recovery apparatus, comprising: an analog-to-digital converter (ADC) (21), a data buffer (22), a digital interpolator (23), a clock phase error estimator (24), a filter (20), and a digital controller (25). Output terminals of the ADC (21) are respectively connected to an input terminal of the data buffer (22) and a first input terminal (26) of the clock phase error estimator (24); the output terminal of the data buffer (22) is connected to a first input terminal (28) of the digital interpolator (23); the output terminal of the digital interpolator (23) is connected to a second input terminal (27) of the clock phase error estimator (24); the output terminal of the clock phase error estimator (24) is connected to the input terminal of the digital controller (25); the output terminal of the digital controller (25) is connected to a second input terminal (29) of the digital interpolator (23). The present invention reduces complexity of circuit design and facilitates the realization of a hardware circuit.

Description

technical field [0001] Embodiments of the present invention relate to communication technologies, and in particular to a clock recovery device. Background technique [0002] In an optical communication system, after the receiving end performs photoelectric conversion, it needs to perform algorithm processing in the digital domain. The rate at which the receiving end performs algorithm processing and the rate at which the transmitting end sends data must be consistent at all times to ensure that all transmitted data is timely. is processed, that is, the transmitter and receiver must ensure clock synchronization. If the clocks of the transmitting end and the receiving end deviate, the clock needs to be recovered to ensure that the sampling data at the receiving end is the sampling data at the best sampling time, so that the data at the receiving end and the transmitting end are kept in sync. [0003] figure 1 It is a structural schematic diagram of a clock recovery device in...

Claims

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Application Information

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IPC IPC(8): H04L7/033
CPCH04B10/60H04L7/0025
Inventor 万文通
Owner HUAWEI TECH CO LTD
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