Clock distribution apparatus used for digital PET detector

Abstract

The invention provides a clock distribution apparatus used for a digital PET detector. The apparatus comprises at least one clock module. Each clock module comprises an active crystal oscillator used for generating a clock signal, a phase-locked loop which is in communication connection with the active crystal oscillator and is used for processing the clock signal and generating a first differential signal, a first clock fan-out buffer in communication connection with the phase-locked loop and a 12-output connector, an FPGA chip which is in communication connection with the 12-output connector and sends a second low-voltage differential signal generated by the FPGA chip to the output connector, a sliding switch which is connected with the FPGA chip to optionally send a relatively high or low level, a light touch switch which is connected with the FPGA chip to send a reset signal, and an input connector connected with the FPGA chip and the second clock fan-out buffer. According to the apparatus, at least 12 synchronous clock signals and synchronous reset signals can be provided, and the clock modules can be cascaded into a tree structure for providing more outputs; and the apparatus is wide in applicability.

Description

technical field [0001] The invention relates to a femtosecond clock distribution device in the field of medical imaging, more particularly to a clock distribution device for digitized PET detectors. Background technique [0002] PET (Positron Emission Tomography, Positron Emission Tomography) imaging technology is a relatively advanced clinical examination imaging technology in the field of nuclear medicine. More and more hospitals have begun to use clinical PET machines for auxiliary diagnosis and treatment. In PET imaging technology, the ideal clock signal is a periodic square wave with a certain amplitude and frequency, which is used to drive various electronic chips containing sequential logic, such as ARM (Acorn RISC Machine) processors, FPGAs and CPUs, etc. , the measurement unit of the frequency of the clock signal adopts the SI unit hertz (Hz). The reset signal refers to a period of high or low level, which is used to reset the sequential logic. For the digital PET ...

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a clock distribution device for digitized PET detectors, thereby solving the problem that a sufficient number of synchronous clock signals or reset signals cannot be provided in the prior art

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