Hybrid main storage architecture based efficient dynamic page scheduling method

A technology of dynamic page and scheduling method, applied in memory system, program startup/switching, resource allocation, etc., can solve problems such as low static power consumption, lack of scheduling strategy in application scenarios, and inability to further develop PCM read power consumption.

Active Publication Date: 2017-09-22
PLA UNIV OF SCI & TECH
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

The active and passive paging algorithm can give full play to the advantages of DRAM and PCM storage media, and the implementation cost is relatively small, but this management method will cause inconsistency in the judgment of read and write heat, and the page migration ratio There will also be differences
These algorithms can effectively take advantage of DRAM write performance and control the number of PCM write operations, but there are generally the following problems: First, it is impossible to effectively avoid frequent and invalid page migration between mixed memory media, resulting in unnecessary system overhead; Second, the prediction effect of data reading and writing tendency in weak locality application scenarios is not good, and inaccurate migra...

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  • Hybrid main storage architecture based efficient dynamic page scheduling method
  • Hybrid main storage architecture based efficient dynamic page scheduling method
  • Hybrid main storage architecture based efficient dynamic page scheduling method

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Embodiment Construction

[0032] The LIRS (Low Inter Reference Recency Set) algorithm is an improved algorithm for the weak locality of LRU. It uses the concept of IRR (Inter-reference recency) to define the number of other pages visited during the last two visits of the same page. , while sorting pages with reference to recency, update the queue according to IRR, so as to accurately grasp the heat of data access in an application environment with weak locality. Wherein, each page corresponds to an entry, and each entry is a structure, that is, a data structure including information such as page address, reading and writing times, and status flags. The IRR of a cache block refers to the number of other non-repeated cache blocks accessed between successive accesses to this block. The non-repeated number of access to other blocks from the latest access to the current time of a block is called the recency of this block. The block is also the page in the present invention. It can be seen that in the stora...

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Abstract

The invention discloses a hybrid main storage architecture based efficient dynamic page scheduling method applied to a memory controller of a horizontal storage architecture which comprises a first storage medium and a second storage medium. The hybrid main storage architecture based efficient dynamic page scheduling method comprises the steps of configuring an access list respectively in each storage medium; configuring a stack respectively for each storage medium in the memory controller; carrying out dynamic management fore recently accessed pages in the storage medium based on the page state records recorded in the stack and the reading-writing access time recorded in the access list, placing the pages with high writing hot-degree in the first storage medium, storing the frequently read pages in the second storage medium, wherein the first storage medium is a DRAM, and the second storage medium is NVM. The hybrid main storage architecture based efficient dynamic page scheduling method can master the historical access information more precisely to adapt to the application scenes with relatively weak locality, can greatly reduce frequent and ineffective page migration quantity between the hybrid memory mediums, and can improve the utilization rate and the access hit rate of a main memory.

Description

technical field [0001] The invention belongs to the field of computer data storage, and in particular relates to a high-efficiency dynamic paging method based on a hybrid main memory architecture. Background technique [0002] DRAM / PCM-based hybrid memory can be roughly divided into two different structures: the "vertical model" that uses DRAM (dynamic random access memory) as a PCM (phase change memory) cache and the "horizontal model" that uses DRAM and PCM as main memory ". The "horizontal model" is a model in which DRAM and PCM constitute the main memory. It uses a unified address space and manages it at the same level. It can make full use of the advantages of the two storage media to effectively allocate data storage space. According to the read and write information in the memory controller Store frequently written data on DRAM, and store read-intensive data on PCM, highlighting the performance advantages of DRAM and taking advantage of the low power consumption of P...

Claims

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Application Information

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IPC IPC(8): G06F9/48G06F9/50G06F12/0882
CPCG06F9/4881G06F9/5016G06F12/0882
Inventor 张震付印金胡谷雨
Owner PLA UNIV OF SCI & TECH
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