A CSP chip with no step electrode structure and its manufacturing method

Abstract

The invention provides a CSP chip without a step electrode structure and a manufacture method thereof, relating to the technical field of chip manufacture. A positive photoresist is spin-coated on the surface of an In-GaN ohmic contact layer of an epitaxial wafer so as to make a mask pattern through exposure and developing; an exposed annular N-GaN limit layer step surface and a center slot are formed by etching at the periphery of the chip; SiO2 is deposited in the center slot and the step surface, and an SiO2 medium membrane layer and an SiO2 conductive hole layer are formed through etching; and a silver mirror layer is evaporated on the outer surface of the step surface and the outer surface of the SiO2 conductive hole layer, and a metal Sn layer is evaporated on the outer surface of the silver mirror layer. According to the method, the Sn layer can be directly heated, so as to package the chip onto a corresponding patch of a package support conveniently; silver glue is not adopted as a binder, so that a complex silver glue dispensing process is omitted, and risks of glue spreading of the silver glue layer and aging and cracking of the silver glue are prevented.

Description

technical field [0001] The invention relates to the technical field of production of light-emitting diodes, especially chips. Background technique [0002] The existing CSP (Chip Scale Package) chip manufacturing process is: sequentially forming N-type layer, P-type layer and DBR (Bragg reflector) layer on the substrate, and then slotting downwards from the DBR (Bragg reflector) layer to N-type layer, and then vapor-deposit metal on the P-side and N-side at the same time to form the P-electrode and N-electrode. The subsequent packaging process is: first coat silver glue on the packaging bracket, and bond the P electrode and N electrode of the chip to the two patch surfaces on the same plane of the packaging bracket located in the cup through the silver glue layer. Since the outer surfaces of the P electrode and the N electrode of the chip formed by the above manufacturing process are not on the same level, the following defects often exist: [0003] 1. There are risks of c...

AI Technical Summary

Problems solved by technology

[0003] 1. There is a risk of chip dumping and incorrect die bonding during packaging

[0004] 2. The amount of coating of the silver glue layer needs to be strictly controlled. Too much coating will cause the silver glue to climb and cover the epitaxial layer, resulting in risks such as leakage, while too little coating will cause sticking effects. bad condition

[0005] 3. Due to the long distance between the P electrode and the N electrode, and the P electrode does not cover the entire epitaxial layer, the current cannot evenly cover the entire interface, so when the current is applied to both ends, the current distribution uniformity will be poor.

[0006] 4. Since the P electrode needs to be made on the DBR (Bragg reflector) layer, in addition to increasing the complexity of the vapor deposition DBR (Bragg reflector) process, the angle of the reflected light on the DBR (Bragg reflector) layer is too small , as long as the light penetrates the DBR (Bragg reflector) layer and reaches the P electrode, it will be absorbed by the electrode, resulting in the disadvantage of the electrode absorbing light

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