Bi-directional bootstrapped dynamic switching circuit with high-voltage device working under low voltage

Abstract

The invention discloses a bi-directional bootstrapped dynamic switching circuit with a high-voltage device working under low voltage, wherein the output end of a second NOT gate is connected with the front end of a first capacitor, the rear end of the first capacitor and the drain of a second PMOS transistor are connected with the source of a third PMOS transistor, both the grid of the third PMOS transistor and the grid of a second NMOS transistor are connected with the output end of the first NOT gate, the grid of the second PMOS transistor, the drain of the third PMOS transistor and the drain of the second NMOS transistor are connected with the grid of a first NMOS transistor; the output end of the first NOT gate is connected with the front end of a second capacitor, the rear end of the second capacitor and the source of the third NMOS transistor are connected with the drain of a fourth NMOS transistor, the grid of a fourth PMOS transistor, the grid of the third NMOS transistor and the grid of the fourth NMOS transistor are connected with the output end of the first NOT gate, and the drain of the fourth PMOS transistor and the drain of the third NMOS transistor are connected with the grid of the first PMOS transistor. According to the circuit provided by the invention, the size of a transmission gate can be effectively reduced, the speed of the transmission gate can be effectively improved, clock feedthrough can be effectively reduced, error can be effectively reduced and accuracy can be effectively improved.

Description

technical field [0001] The invention relates to a circuit structure for realizing high-speed switching in a low-voltage environment, in particular to a bidirectional bootstrap dynamic switching circuit in which a high-voltage device operates at a low voltage. Background technique [0002] In the prior art, the common CMOS switch transmission gate circuit is composed of a PMOS transistor and an NMOS transistor, please refer to figure 1 , by adding ENN (VDDA) to the Gate pole of the NMOS transistor and ENP (VSSA) to the Gate pole of the PMOS transistor to realize low-impedance conduction input and output, when the input and output voltages are constant, the higher the power supply voltage of the circuit, the higher the transmission The smaller the on-resistance of the gate, the faster the transmission speed. When designing a high-speed switched-capacitor circuit, the on-resistance of the transmission gate circuit must be low enough if the signal needs to be transmitted quickl...

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Problems solved by technology

[0010] Since the fingerprint identification chip is designed as a 5V medium-voltage device, the minimum operating voltage is only about 2.4V, and the V of the 5V device TH It is close to 1.0V, so if a conventional transmission gate is used, the size of the NMOS tube and the PMOS tube will be very large, which will bring the following disadvantages: first, the size and area of ​​the NMOS tube and the PMOS tube of the transmission gate are large; , due to the large area of ​​the transmission gate circuit, the corresponding parasitic capacitance and other parameters are also large, which affects the speed of the transmission gate; at the same time, the large size also brings high cost problems. In addition, due to the large size of the transmission gate, the closing When turned on, it will cause a large clock feedthrough, which will increase the error and reduce the accuracy

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