Design method for clock management framework of low-power multi-core SoC

Abstract

The invention discloses a design method for a clock management framework of a low-power multi-core SoC. A PLL (phase-locked loop) circuit is integrated in an SoC chip; an input clock is subjected to frequency doubling to obtain a high-frequency clock required in the SoC chip; the clock subjected to the frequency doubling is subjected to frequency division of different multiples through a frequency divider according to application configuration information to obtain working clocks required by all modules in the SoC chip; the selection of a clock source is controlled through an external port CLKMODE, and an external clock source mode or a PLL mode is selected; meanwhile, whether the PLL mode is enabled or not is configured by a register; and a main DSP core performs configuration on a low-power control register according to clock enable signals of DSP cores 1, 2 and 3, and a clock enable signal of the main DSP core is valid for a long term. According to the method, an internal PLL can flexibly configure the internal working clocks to reduce the input clock frequency of a PCB.

Description

technical field [0001] The invention belongs to the technical field of chip clock management design and implementation methods in semiconductor integrated circuits, and in particular relates to a multi-core SoC system-on-chip clock low-power management design method. Background technique [0002] Basically, in all electronic systems and integrated circuit fields, clock signals are used for timing control. With the increasing complexity of SoC chip design, its internal clock design is also becoming more and more complex. SoC chips are generally based on a certain bus architecture, and microprocessors, memories, I / O interface modules and other specialized functions are integrated on the bus. Processing modules, etc. There are usually several clock domains inside an SoC chip, and the clock management circuit can be described as the basic component of the SoC. configuration management, etc. [0003] Due to its high operating frequency and high system integration, the multi-cor...

AI Technical Summary

Problems solved by technology

[0003] Due to its high operating frequency and high system integration, the multi-core SoC system chip has a large increase in power consumption, which will bring a series of practical problems: First, the increase in SoC operating temperature caused by the increase in power consumption will cause semiconductor parameters Drift affects the normal operation of the SoC chip, reduces chip reliability and increases the risk of chip failure; secondly, the rise in SoC operating temperature caused by the increase in power consumption will shorten the life of the chip and limit the further improvement of system performance

Images