Packaging structure and packaging method of back-illuminated cmos sensor

A CMOS sensor and packaging structure technology, which is applied in the field of back-illuminated CMOS sensor packaging structure, can solve the problems of low product yield, low device stability, large packaging volume of image sensor chips and logic chips, etc., and achieve improved packaging performance , saving process cost, high sensing performance and device reliability

Active Publication Date: 2022-03-01
SJ SEMICON JIANGYIN CORP
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Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a packaging structure and packaging method for a back-illuminated CMOS sensor, which is used to solve the problem that the packaging volume of the image sensor chip and the logic chip in the prior art is large and the device Problems of low stability and low product yield

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  • Packaging structure and packaging method of back-illuminated cmos sensor
  • Packaging structure and packaging method of back-illuminated cmos sensor
  • Packaging structure and packaging method of back-illuminated cmos sensor

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Embodiment Construction

[0047] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] see Figure 1 to Figure 15. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the ...

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Abstract

The invention provides a packaging structure and packaging method of a back-illuminated CMOS sensor, comprising: a rewiring layer; a back-illuminated CMOS sensor structure fixedly connected to the second surface of the rewiring layer; a logic chip arranged on the The first surface of the rewiring layer; packaging material, covering the logic chip; perforation, formed in the packaging material; metal lead structure, made in the through hole, so as to realize the rewiring layer, the The back-illuminated CMOS sensor structure is electrically derived from the logic chip. The present invention adopts the method of rewiring layer to realize the electrical connection between the back-illuminated CMOS sensor, the logic chip and the metal lead structure, and has the advantages of small packaging volume, high sensing performance and device reliability; The electrical extraction of the rewiring layer can be achieved by opening holes in the packaging material, without the need for silicon through holes and other processes, which can greatly save process costs.

Description

technical field [0001] The invention belongs to the field of semiconductor packaging, in particular to a packaging structure and packaging method of a back-illuminated CMOS sensor. Background technique [0002] With the increasingly powerful functions of integrated circuits, higher performance and higher integration, and the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and in the value of the entire electronic system The proportion is increasing. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors are developing towards higher density and higher clock frequency, and packaging is also developing towards higher density. [0003] Due to the advantages of miniaturization, low cost and high integration, as well as better performance and higher energy efficiency, fan-out wafer-level packaging (fowlp) technology has become a An important packaging m...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/146
CPCH01L27/14634H01L27/14636H01L27/1464H01L27/14683H01L27/1469H01L2224/96H01L2224/04105H01L2224/12105
Inventor 陈彦亨林正忠
Owner SJ SEMICON JIANGYIN CORP
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