Transistor and method for preparing the same, and semiconductor memory device and method for preparing the same
A technology of storage devices and transistors, which is applied in the manufacture of semiconductor/solid-state devices, semiconductor devices, electrical components, etc., can solve the problems of easy generation of voids in SOD, bridging and short circuit in plug conductive layers, and device failure, etc., so as to enhance physical adsorption capacity , Reduce voids, reduce the effect of component parasitic resistance and parasitic capacitance
Pending Publication Date: 2017-12-22
CHANGXIN MEMORY TECH INC
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Problems solved by technology
[0003] In view of the above-mentioned shortcoming of prior art, the object of the present invention is to provide a kind of transistor and preparation method thereof, semiconductor storage device and preparation method thereof, be used to solve easily produce void in SOD spin-coating deposition process in the prior art, Causes a bridging short circuit between the plug conductive layers, which leads to the failure of the device
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[0081] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.
[0082] see Figure 1 to Figure 11 , the first embodiment of the present invention relates to a method for manufacturing a transistor, which at least includes:
[0083] Such as figure 1 As shown, a substrate 100 is provided, and a gate structure 200 is prepared on the substrate 100; as figure 2 As shown, a first sidewall insulating material 300 covering the gate structure 200 and the substrate 100 is formed on the substrate 100, and...
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The invention provides a transistor and a method for preparing the same, and a semiconductor memory device and a method for preparing the same. The method for preparing the transistor at least comprises: a substrate is provided and a gate structure is prepared on the substrate; a first side wall insulating layer and a surface polarity modifying layer are formed on the substrate, wherein the first side wall insulating layer covers the gate structure and the surface polarity modifying layer covers the first side wall insulating layer; an insulating medium isolation layer is formed on the substrate, wherein the insulating medium isolation layer covers the surface polarity modifying layer; and plug conductive layers arranged at the two sides of the insulating medium isolation layer are formed on the substrate. According to the invention, on the basis of direct contact between the surface polarity modifying layer and the insulating medium isolation layer, the surface adsorption force for the precursor of the insulating medium isolation layer is enhanced and generation of holes in the insulating medium isolation layer is reduced, so that the bridging short circuit between the plug conductive layers is avoided.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a transistor and a preparation method thereof, a semiconductor storage device and a preparation method thereof. Background technique [0002] Metal Oxide Semiconductor Field Effect Transistor (MOSFET, Metallic Oxide Semiconductor Field Effect Transistor) is a transistor widely used in integrated circuits, and its process layout is also widely used in integrated circuits. In the MOSFET structure, an insulating dielectric isolation layer is usually covered on the periphery and above the gate structure, and the sidewall insulating layer formed on the side wall of the insulating dielectric isolation layer is used to isolate the plug conductor layer from the gate conductive layer in the gate structure, In order to avoid the short circuit of the two conductive layers and cause the device (Device) to fail. Moreover, in order to have a good insulation capability between the condu...
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IPC IPC(8): H01L29/78H01L21/336H01L21/02H01L29/423
CPCH01L29/42364H01L29/66477H01L29/78H01L21/02107
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC