A chip double-sided packaging structure and its manufacturing method
A technology of packaging structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve real-time adjustment of chip model and type, poor flexibility of chip function configuration, and inability to meet individualization Issues such as ordering, to achieve the effect of balancing thermal expansion coefficient, stable terminal connection, and preventing chip breakage
Active Publication Date: 2018-09-21
CHANGXIN MEMORY TECH INC
View PDF5 Cites 0 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Since the memory chip 203 and the cache chip 201 are stacked on the same side of the substrate 200, the thickness of the packaging structure becomes larger
At the same time, the packaging structure manufactured by the above method needs to be completely packaged at one time during the production process, so not only the production cycle is too long, but also the flexibility of chip function configuration is poor, and the model and type of each chip cannot be adjusted in real time according to user needs. Meet the needs of personalized ordering
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0059] In the following, only some exemplary embodiments are briefly described. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature and not restrictive.
[0060] In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Back", "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner", "Outer", "Clockwise", "Counterclockwise", "Axial" , "radial", "circumferential" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or im...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The invention relates to a chip double-sided packaging structure and a manufacturing method thereof. The packaging structure includes: the memory chip stack body is arranged on the substrate, the first rewiring layer is formed on the memory chip stack body; the buffer chip is arranged on the surface of the substrate; the terminal is arranged on the substrate; the first plastic package seals the memory chip stack body; 2. The plastic package seals the connection between the cache chip and the terminal and the substrate. The manufacturing method includes: arranging the memory chip stack body on the substrate; forming a first plastic package to seal the memory chip stack body; setting the cache chip on the substrate; forming a second plastic package to seal the cache chip; Thinning: Drilling holes in the second plastic package, implanting terminals connected to the metal pads in the drilling holes, and welding and fixing them. The chip stack three-dimensional package structure of the present invention has small overall structural size, short signal transmission distance, and can flexibly configure performance according to usage requirements.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chip double-sided packaging structure and a manufacturing method thereof. Background technique [0002] In the existing multi-chip packaging structure, each chip is packaged on one side of the substrate, such as figure 1 As shown, the existing multi-chip stack package structure includes a substrate 200, a cache chip 201 is arranged on one side of the substrate 200, the cache chip 201 is electrically connected to the substrate 200 through a redistribution layer 202, and stacked on the surface of the cache chip 201 A memory chip 203 is provided, and a plastic package 204 is formed on the side surface of the substrate 200 to seal the buffer chip 201 and the memory chip 203 , thereby forming a single-side molded form. On the other side surface of the substrate 200, a ball grid array terminal 205 is arranged, and the ball grid array terminal 205 is electrically connected to ...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/56H01L23/31H01L25/065
CPCH01L2924/181H01L2224/16145H01L2924/00012
Inventor 庄凌艺
Owner CHANGXIN MEMORY TECH INC