A kind of semiconductor device and its manufacturing method

Abstract

A semiconductor device and its manufacturing method, the semiconductor device comprises from bottom to top: a silicon substrate; one or more NAND strings formed above the silicon substrate; one or more NAND strings formed above the NAND string a plurality of peripheral devices; a single crystal silicon layer formed over the one or more peripheral devices, and one or more first interconnects formed between the one or more peripheral devices and the one or more NAND strings Floor. The peripheral device and the array device are bonded through an adhesive interface. The present invention separates the manufacturing of the array device and the peripheral device, so as to avoid the mutual influence of the two devices on the manufacturing process of each other, thus solving the problem in the prior art that the manufacturing of the latter layer is limited by the temperature after the manufacturing of the former layer. Thus, good peripheral device performance is obtained. In addition, since the peripheral devices are stacked on the array device, high device density is realized.

Description

technical field [0001] The invention relates to a semiconductor device and a preparation method thereof, in particular to a semiconductor device forming a 3D NAND flash memory and a preparation method thereof. Background technique [0002] With the continued emphasis on highly integrated electronics, there is a continuing need for semiconductor memory devices that operate at higher speeds and lower power and have increased device densities. To this end, devices with smaller dimensions and multilayer devices with transistor cells arranged in horizontal and vertical arrays have been developed. 3D NAND is an emerging type of flash memory developed by the industry. It solves the limitations of 2D or planar NAND flash memory by stacking memory particles together. [0003] The planar structure of NAND flash memory is approaching its actual expansion limit, which brings severe challenges to the semiconductor memory industry. The new 3D NAND technology stacks multiple layers of da...

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Problems solved by technology

[0006] However, the disadvantage of the above-mentioned patented technology is that the above-mentioned vertical channel memory device is fabricated sequentially on only one Si substrate layer, so the temperature of the subsequent layers must be limited during fabrication, otherwise the previously fabricated ones will be destroyed due to the high temperature. Layer produces ion diffusion, which affects product performance

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