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Formation method of semiconductor structure

A semiconductor and layer-forming technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, and electrical solid-state devices, etc., can solve problems such as the decline of electrical properties of semiconductor structures, and achieve the effect of improving electrical properties

Active Publication Date: 2020-06-09
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the contact holes formed in the prior art easily lead to a decrease in the electrical performance of the semiconductor structure

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Embodiment Construction

[0031] It can be seen from the background art that the contact holes formed in the prior art may easily lead to a decrease in the electrical performance of the semiconductor structure. combined reference figure 1 The electron microscope image of the contact hole is shown to analyze the reasons for the decline in the electrical performance of the semiconductor structure. The electron microscope diagram shows the adjacent first contact hole 110 and the second contact hole 120. As the process node of the integrated circuit continues to shrink, the distance between the first contact hole 110 and the second contact hole 120 gradually decreases. Therefore, during the process of forming the first contact hole 110 and the second contact hole 120, the size of the photoresist layer along the direction parallel to the surface of the substrate is also getting smaller and smaller, especially in the The photoresist layer on the mask material layer between the first contact hole 110 and the...

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Abstract

A method for forming a semiconductor structure, comprising: providing a substrate; forming a gate structure on the substrate; forming source and drain doped regions in the substrate on both sides of the gate structure; forming an interlayer dielectric layer on the source and drain doped regions; A mask layer having a plurality of first openings is formed on the interlayer dielectric layer, the first openings penetrate the mask layer, and the first openings are rectangular along a cross section parallel to the surface of the substrate, and the long sides of the first openings have a first length; Wherein, the direction parallel to the long side of the first opening is the extension direction of the first opening; the mask layer is subjected to surface treatment to remove part of the mask layer to increase the first length; the interlayer dielectric layer is etched using the mask layer as a mask , forming a contact hole exposing the source-drain doped region in the interlayer dielectric layer. The present invention performs surface treatment on the mask layer to increase the first length of the first opening, thereby increasing the length dimension of the contact hole along the extension direction, thereby avoiding the difficulty in exposing the source and drain due to the too small length dimension of the contact hole along the extension direction The problem of doped regions.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a semiconductor structure. Background technique [0002] Integrated circuit fabrication requires the use of multiple metal layers to connect individual semiconductor devices together to form circuits. Specifically, the metal layer includes interconnection lines and contact hole plugs formed in the contact holes, the contact hole plugs in the contact holes connect semiconductor devices, and the interconnection lines connect contact hole plugs on different semiconductor devices to form circuit. [0003] The method for forming the contact hole includes the following steps: providing a substrate, the substrate including adjacent first and second regions; forming a gate structure on the substrate of the first and second regions; A first source-drain doped region is formed in the substrate on both sides of the gate structure in a region, and a second source-drain do...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/336
CPCH01L21/768H01L21/76897H01L29/66795H01L21/76816H01L21/76831H01L21/823418H01L21/823431H01L21/823437H01L27/0886
Inventor 张城龙郑喆张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP
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