Double-sided-folded gate-controlled source/drain double tunneling type bidirectional conductive transistor and manufacturing method thereof
A bidirectional conduction, source-drain technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems that transistors can only be used as one-way switches and sub-threshold swings cannot be reduced, and achieve excellent gate electrodes Control ability, effect of low subthreshold swing
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- Publication Date
- 2018-03-16
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Abstract
Description
technical field
[0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, in particular to a double-sided folding gate-controlled source-drain double-tunneling bidirectional conduction transistor with low leakage current suitable for low-power integrated circuit manufacturing and a manufacturing method thereof. Background technique
[0002] According to the requirements of Moore's law, the basic unit MOSFETs of integrated circuits will become smaller and smaller in size, which will not only increase the difficulty of the manufacturing process, but also cause various adverse effects to become more prominent. Due to the limitations of the physical mechanism of current generation in the MOSFETs used in IC design today, the subthreshold swing cannot be lower than 60mV / dec. When the ordinary tunneling field effect transistor is used as a switching device, the tunneling effect of carriers between the semiconductor energy bands is used as the ...
Examples
Embodiment Construction
[0096] Below in conjunction with accompanying drawing, the present invention will be further described:
[0097] Such as figure 1 , figure 2 and image 3 As shown, a double-side folded gate-controlled source-drain double-tunneling bidirectional conduction transistor includes a silicon substrate 12 of an SOI wafer, and a substrate insulating layer 11 of the SOI wafer is above the silicon substrate 12 of the SOI wafer. , above the substrate insulating layer 11 of the SOI wafer is a single crystal silicon film 1, a barrier adjustment gate 2, a partial area of the gate electrode insulating layer 7 and a partial area of the insulating dielectric barrier layer 13; wherein, the single crystal silicon thin film 1 For impurity concentration below 10 16 cm -3 The monocrystalline silicon semiconductor material has a U-shaped groove structure; the heavily doped source-drain interchangeable region a5 and the heavily doped source-drain interchangeable region b6 perform ion implanta...