Gate oxide layer structure and manufacturing method of shielded gate trench mosfet

Abstract

The invention relates to a gate oxide layer structure of a shielded gate trench MOSFET and a manufacturing method thereof. The thickness of the oxide layer between the gate and the source is adjusted by one borophosphosilicate glass deposition and two reflow processes, so as to avoid the root oxide layer between the gate and the source. Unevenness, resulting in device failure or abnormal parameters. The invention fills the polysilicon with the deep groove, and the two deep grooves balance the mutual charge to complete the super junction function, and then forms the shallow groove above the deep groove by wet etching, and fabricates the shielding gate trench MOSFET in the shallow groove to form the shielding gate together. Trench devices can be realized with traditional semiconductor manufacturing processes, improving the quality of the oxide layer between the first polysilicon and the gate polysilicon without increasing the difficulty of the process, optimizing product parameters, improving yield and reliability, and finally To reduce chip cost.

Description

technical field [0001] The invention belongs to the technical field of semiconductor power devices, and in particular relates to a gate oxide layer structure and a manufacturing method of a shielded gate trench MOSFET. Background technique [0002] For traditional power MOSFET devices, there is a certain trade-off relationship between device on-resistance (Ron) and source-drain breakdown voltage (Ron∝BV 2.5 ), has limited the development of power MOSFET devices for a long time. The shielded gate trench MOSFET uses the principle of charge balance, so that the N-type drift region can achieve a higher breakdown voltage of the device even in the case of a higher doping concentration, thereby obtaining a low on-resistance, breaking the traditional power MOSFET. Silicon limit. Such as Figure 20 , The quality of the oxide layer formed by highly doped polysilicon in the common process flow is not high, and the thickness of the oxide layer between the gate and source polarities is...

AI Technical Summary

Problems solved by technology

like Figure 20 , the ordinary process flow of highly doped polysilicon forms an oxide layer of low quality and the thickness of the oxide layer between the gate and source polarities is uneven, which brings great risks to device parameters and reliability

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