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Storage node contact manufacturing method of semiconductor device and semiconductor device

A storage node and semiconductor technology, applied in the manufacture of semiconductor/solid-state devices, semiconductor devices, electric solid-state devices, etc., can solve the problems of large contact resistance, unstable growth of the metal bonding layer at the contact interface, and the device cannot work normally. The effect of improving performance

Pending Publication Date: 2018-04-13
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] As the semiconductor contact manufacturing process becomes finer, and the storage node contact is formed on the semiconductor substrate, so that the interval between the nodes becomes narrower than before the design rule is reduced, the distance between the storage node contact and the storage node contact area Insufficient contact between them will lead to unstable growth of the metal bonding layer at the contact interface, resulting in a large contact resistance, which will adversely affect the performance of the memory. When the impact is severe, the device cannot work normally.

Method used

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  • Storage node contact manufacturing method of semiconductor device and semiconductor device
  • Storage node contact manufacturing method of semiconductor device and semiconductor device
  • Storage node contact manufacturing method of semiconductor device and semiconductor device

Examples

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Embodiment 1

[0099] Such as Figure 1 to Figure 8 As shown, in this embodiment, a method for manufacturing storage node contacts in a semiconductor device is formed such as figure 1 The method of the semiconductor device shown specifically includes as figure 2 The steps shown include:

[0100] Step S01: if image 3 As shown, a semiconductor substrate 100 is provided, and an active region 101, a trench isolation structure 102 for isolating each of the active regions 101, a plurality of word lines 110, and a plurality of word lines 110 are formed in the semiconductor substrate 100, and in the semiconductor substrate 100 A plurality of bit lines 120 are formed on the substrate; as Figure 4 As shown, a bit line isolation structure is formed on the semiconductor substrate 100 to cover the bit line 120 .

[0101] Step S02: if Figure 5 As shown, the active region 101 between the bit line isolation structures is etched to expose the source region of the active region 101 to form a contact ...

Embodiment 2

[0133] In this embodiment, a method for manufacturing a storage node contact in a semiconductor device includes:

[0134] Such as image 3 As shown, a semiconductor substrate 100 is provided, and a plurality of rod-shaped active regions 101, a trench isolation structure 102 for isolating each rod-shaped active region 101, a plurality of word lines 110, and a plurality of word lines 110 are formed in the semiconductor substrate 100. A plurality of bit lines 120 are formed on the semiconductor substrate 100; the trench isolation structures 102 are formed between the rod-shaped active regions 101, and the rod-shaped active regions 101 and the trench isolation structures 102 are arranged alternately along the first direction. On the semiconductor substrate 100, the word line 110 is buried in the semiconductor substrate 100 along a second direction, and the first direction and the second direction intersect, and the bit line 120 is buried along a third direction formed on the surf...

Embodiment 3

[0152] A semiconductor device in this embodiment includes:

[0153] A semiconductor substrate 100, wherein an active region 101, a trench isolation structure 102 for isolating each of the active regions 101, a plurality of word lines 110, and a plurality of bit lines are formed on the semiconductor substrate 100. line 120;

[0154] A bit line isolation structure, formed on the semiconductor substrate 100 and covering the bit line 120; wherein, a contact window 150 is formed on the active region 101, formed between the bit line isolation structures, and the The bottom of the contact window 150 exposes the source region of the active region 101;

[0155] a source contact 160, disposed on the source region of the active region 101 outside the two adjacent word lines 110 and located at the bottom of the contact window 150;

[0156] The partition wall 170 is formed on the side wall of the bit line isolation structure in the contact window 150, and an extended gap 190 is formed be...

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Abstract

The invention provides a storage node contact manufacturing method of a semiconductor device and the semiconductor device. The method comprises steps that an active region, a trench isolation structure, a word line and bit lines are formed in a semiconductor substrate, a contact window is formed between the bit lines, source contacts and a partition wall are formed in the contact window, the source contacts are partially removed to make the area of an end surface exposed by the source contacts larger than the area enclosed by the partition wall, and storage node contact is formed. The semiconductor device comprises the active region, the trench isolation structure, the word line and the bit lines which are formed in the semiconductor substrate, wherein the contact window is formed betweenthe bit lines, the contact window is provided with the source contacts and the partition wall, an expansion area is formed between the source contacts and the partition wall to make the area of the end surface exposed by the source contacts larger than the area enclosed by the partition wall, and storage node contact is formed. The method and the device are advantaged in that through increasing the contact area of the end surface exposed by the source contacts, the contact area of a bonding layer of a storage node contact and the source contacts is maximized, and conductive performance of theconductive device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing storage node contacts in a semiconductor device and the semiconductor device. Background technique [0002] A memory typically includes a storage capacitor for storing charge representing stored information and a storage transistor connected to the storage element. An active region, a drain region and a gate structure are formed in the storage transistor. The gate structure is connected to a word line for controlling current flow between the source and drain regions. The source area is used to form a bit line contact area to be connected to the bit line, and the drain area is used to form a storage node contact area to be connected to the storage capacitor. Wherein, when connecting the storage node contact region to the storage capacitor, it is usually necessary to form a storage node contact on the storage node contact region, so as to real...

Claims

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Application Information

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IPC IPC(8): H01L27/108H01L21/768
CPCH01L21/76895H10B12/30
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC
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